专利检索 ap:("INTEL Corporation") AND inv:"ANDREI, Valentin" 第 1 页

1.

发明公开
PREEMPTIVE PAGE FAULT HANDLING 审中-公开

公开(公告)号：EP3938902A1

公开(公告)日：2022-01-19

申请号：EP20712086.6

申请日：2020-02-10

申请人： INTEL Corporation

发明人： RAMADOSS, Murali , VEMULAPALLI, Vikranth , COORAY, Niran , SADLER, William B. , PEARCE, Jonathan D. , PETRE, Marian Alin , ASHBAUGH, Ben , OULD-AHMED-VALL, ElMoustapha , GALOPPO VON BORRIES, Nicolas , KOKER, Altug , ANANTARAMAN, Aravindh , MAIYURAN, Subramaniam , GEORGE, Varghese , KIM, Sungye , ANDREI, Valentin

IPC分类号： G06F9/50 , G06F12/08

2.

发明公开
SYSTEMS AND METHODS FOR CACHE OPTIMIZATION 审中-公开

公开(公告)号：EP3938893A1

公开(公告)日：2022-01-19

申请号：EP20718900.2

申请日：2020-03-14

申请人： INTEL Corporation

发明人： KOKER, Altug , RAY, Joydeep , OULD-AHMED-VALL, Elmoustapha , APPU, Abhishek , ANANTARAMAN, Aravindh , ANDREI, Valentin , BILAGI, Durgaprasad , GEORGE, Varghese , INSKO, Brent , JAHAGIRDAR, Sanjeev , JANUS, Scott , K, Pattabhiraman , KIM, SungYe , MAIYURAN, Subramaniam , RANGANATHAN, Vasanth , STRIRAMASSARMA, Lakshminarayanan , TIAN, Xinmin

IPC分类号： G06F9/38 , G06F12/0862 , G06F9/30 , G06F12/123 , G06F12/126

3.

发明公开
MEMORY CONTROLLER MANAGEMENT TECHNIQUES 审中-公开

公开(公告)号：EP4270201A3

公开(公告)日：2024-01-31

申请号：EP23197619.2

申请日：2020-03-14

申请人： INTEL Corporation

发明人： APPU, Abhishek R , ANANTARAMAN, Aravindh , OULD-AHMED-VALL, ElMoustapha , ANDREI, Valentin , GALOPPO VON BORRIES, Nicolas , GEORGE, Varghese , KOKER, Altug , MACPHERSON, Mike , MAIYURAN, Subramaniam , RAY, Joydeep , PAPPU, Lakshminarayana , GARCIA, Guadalupe

IPC分类号： G06F12/02 , G06F12/0804 , G06F12/0862 , G06F12/0893 , G06F12/06 , G06F12/0811 , G06F12/0875 , G06F12/0866 , G06F12/0895 , G06F15/173 , G06F7/58 , G06F16/27 , G06F16/245 , G06F16/2453 , G06F9/38 , G06F9/30 , G06F9/50 , G06F12/12 , G06F12/128

摘要： Methods and apparatus relating to memory controller techniques. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, and a processor communicatively coupled to the cache memory and the high-bandwidth memory, the processor to manage data transfer between the cache memory and the high-bandwidth memory for memory access operations directed to the high-bandwidth memory. Other embodiments are also disclosed and claimed.

4.

发明公开
SYSTEMS AND METHODS FOR EXPLOITING QUEUES AND TRANSITIONAL STORAGE FOR IMPROVED LOW-LATENCY HIGH-BANDWIDTH ON-DIE DATA RETRIEVAL 审中-公开

公开(公告)号：EP3938906A1

公开(公告)日：2022-01-19

申请号：EP20714753.9

申请日：2020-02-24

申请人： INTEL Corporation

发明人： ANANTARAMAN, Aravindh , KOKER, Altug , GEORGE, Varghese , MAIYURAN, Subramaniam , KIM, SungYe , ANDREI, Valentin

IPC分类号： G06F9/54 , G06F9/50

5.

发明公开
GRAPHICS PROCESSOR DATA ACCESS AND SHARING 审中-公开

公开(公告)号：EP3938895A1

公开(公告)日：2022-01-19

申请号：EP20718906.9

申请日：2020-03-14

申请人： INTEL Corporation

发明人： KOKER, Altug , GEORGE, Varghese , ANANTARAMAN, Aravindh , ANDREI, Valentin , APPU, Abhishek R. , COORAY, Niranjan , GALOPPO VON BORRIES, Nicolas , MACPHERSON, Mike , MAIYURAN, Subramaniam , OULD-AHMED-VALL, ElMoustapha , PUFFER, David , RANGANATHAN, Vasanth , RAY, Joydeep , SHAH, Ankur N. , STRIRAMASSARMA, Lakshminarayanan , SURTI, Prasoonkumar , TANGRI, Saurabh

IPC分类号： G06F9/38 , G06F12/0862 , G06F9/30

6.

发明公开
SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES 审中-公开

公开(公告)号：EP3938892A2

公开(公告)日：2022-01-19

申请号：EP20715533.4

申请日：2020-02-24

申请人： INTEL Corporation

发明人： ANDREI, Valentin , MAIYURAN, Subramaniam , KIM, SungYe , GEORGE, Varghese , KOKER, Altug , ANANTARAMAN, Aravindh

IPC分类号： G06F9/38

7.

发明公开
SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE 审中-公开

公开(公告)号：EP3938889A1

公开(公告)日：2022-01-19

申请号：EP20718908.5

申请日：2020-03-14

申请人： INTEL Corporation

发明人： RAY, Joydeep , JANUS, Scott , GEORGE, Varghese , MAIYURAN, Subramaniam , KOKER, Altug , APPU, Abhishek , SURTI, Prasoonkumar , RANGANATHAN, Vasanth , ANDREI, Valentin , GARG, Ashutosh , HAREL, Yoav , HUNTER, JR., Arthur , KIM, SungYe , MACPHERSON, Mike , OULD-AHMED-VALL, Elmoustapha , SADLER, William , STRIRAMASSARMA, Lakshminarayanan , VEMULAPALLI, Vikranth

IPC分类号： G06F9/30 , G06F9/38

8.

发明公开
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE 审中-公开

公开(公告)号：EP3938888A1

公开(公告)日：2022-01-19

申请号：EP20718907.7

申请日：2020-03-14

申请人： INTEL Corporation

发明人： SURTI, Prasoonkumar , MAIYURAN, Subramaniam , ANDREI, Valentin , APPU, Abhishek , GEORGE, Varghese , KOKER, Altug , MACPHERSON, Mike , OULD-AHMED-VALL, Elmoustapha , RANGANATHAN, Vasanth , RAY, Joydeep , STRIRAMASSARMA, Lakshminarayanan , KIM, SungYe

IPC分类号： G06F9/30

9.

发明公开
MEMORY CONTROLLER MANAGEMENT TECHNIQUES 审中-公开

公开(公告)号：EP4270201A2

公开(公告)日：2023-11-01

申请号：EP23197619.2

申请日：2020-03-14

申请人： INTEL Corporation

发明人： APPU, Abhishek R , ANANTARAMAN, Aravindh , OULD-AHMED-VALL, ElMoustapha , ANDREI, Valentin , GALOPPO VON BORRIES, Nicolas , GEORGE, Varghese , KOKER, Altug , MACPHERSON, Mike , MAIYURAN, Subramaniam , RAY, Joydeep , PAPPU, Lakshminarayana , GARCIA, Guadalupe

IPC分类号： G06F12/06

摘要： Methods and apparatus relating to memory controller techniques. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, and a processor communicatively coupled to the cache memory and the high-bandwidth memory, the processor to manage data transfer between the cache memory and the high-bandwidth memory for memory access operations directed to the high-bandwidth memory. Other embodiments are also disclosed and claimed.

10.

发明公开
DYNAMIC MEMORY RECONFIGURATION 审中-公开

公开(公告)号：EP3938914A1

公开(公告)日：2022-01-19

申请号：EP20718903.6

申请日：2020-03-14

申请人： INTEL Corporation

发明人： RAY, Joydeep , COORAY, Niranjan , MAIYURAN, Subramaniam , KOKER, Altug , SURTI, Prasoonkumar , GEORGE, Varghese , ANDREI, Valentin , APPU, Abhishek , GARCIA, Guadalupe , K, Pattabhiraman , KIM, SungYe , KUMAR, Sanjay , MAROLIA, Pratik , OULD-AHMED-VALL, Elmoustapha , RANGANATHAN, Vasanth , SADLER, William , STRIRAMASSARMA, Lakshminarayanan

IPC分类号： G06F12/0804 , G06F12/0893 , G06F12/0862 , G06F9/38 , G06F12/12 , G06F12/128