公开(公告)号：EP4325371A2

公开(公告)日：2024-02-21

申请号：EP23217515.8

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： COORAY, Niranjan L. ,  APPU, Abhishek R. ,  KOKER, Altug ,  RAY, Joydeep ,  VEMBU, Balaji ,  K, Pattabhiraman ,  PUFFER, David ,  COWPERTHWAITE, David J. ,  SANKARAN, Rajesh M. ,  SINGH, Satyeshwar ,  KP, Sameer ,  SHAH, Ankur N. ,  TIAN, Kun

IPC: G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：EP3401874A1

公开(公告)日：2018-11-14

申请号：EP18159601.6

申请日：2018-03-01

Applicant: INTEL Corporation

Inventor： KOKER, Altug ,  WALD, Ingo ,  PUFFER, David ,  MAIYURAN, Subramaniam M. ,  SURTI, Prasoonkumar ,  VEMBU, Balaji ,  LUEH, Guei-Yuan ,  RAMADOSS, Murali ,  APPU, Abhishek R. ,  RAY, Joydeep

IPC: G06T1/20 ,  G06F9/46 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06T1/20 ,  G06F9/3009 ,  G06F9/30185 ,  G06F9/3851 ,  G06F9/461 ,  G06F9/4843

Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.

公开(公告)号：EP3385847A1

公开(公告)日：2018-10-10

申请号：EP18160824.1

申请日：2018-03-08

Applicant: INTEL Corporation

Inventor： RAY, Joydeep ,  KOKER, Altug ,  VALERIO, James A. ,  PUFFER, David ,  APPU, Abhishek R. ,  JUNKINS, Stephen

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0888 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/621 ,  G06T1/60

Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.

公开(公告)号：EP4235441A1

公开(公告)日：2023-08-30

申请号：EP23151691.5

申请日：2023-01-16

Applicant: INTEL Corporation

Inventor： PAL, Rahul ,  BALLE, Susanne M. ,  PUFFER, David ,  CHITLUR, Nagabhushan

IPC: G06F12/0831 ,  G06F12/0888 ,  G06F13/40 ,  G06F13/42 ,  G06F3/06 ,  G06F12/0813 ,  G06F12/02

Abstract: In an embodiment, an apparatus includes: a first downstream port to couple to a first peer device; a second downstream port to couple to a second peer device; and a peer-to-peer (PTP) circuit to receive a memory access request from the first peer device, the memory access request having a target associated with the second peer device, where the PTP circuit is to convert the memory access request from a coherent protocol to a memory protocol and send the converted memory access request to the second peer device. Other embodiments are described and claimed.

公开(公告)号：EP3938915A1

公开(公告)日：2022-01-19

申请号：EP20719251.9

申请日：2020-03-14

Applicant: INTEL Corporation

Inventor： APPU, Abhishek R. ,  KOKER, Altug ,  ANANTARAMAN, Aravindh ,  OULD-AHMED-VALL, ElMoustapha ,  ANDREI, Valentin ,  GALOPPO VON BORRIES, Nicolas ,  GEORGE, Varghese ,  MACPHERSON, Mike ,  MAIYURAN, Subramaniam ,  RAY, Joydeep ,  STRIRAMASSARMA, Lakshminarayanan ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  SINHA, Kamal ,  HUNTER, Arthur ,  SURTI, Prasoonkumar ,  PUFFER, David ,  VALERIO, James ,  SHAH, Ankur N.

IPC: G06F12/0811 ,  G06F12/0875 ,  G06F16/27 ,  G06F12/0866 ,  G06F16/2453

公开(公告)号：EP3392828B1

公开(公告)日：2020-03-04

申请号：EP18168630.4

申请日：2018-04-20

Applicant: INTEL Corporation

Inventor： MAIYURAN, Subramaniam M. ,  LUEH, Guei-Yuan ,  PAL, Supratim ,  CHEN, Gang ,  KOMMARAJU, Ananda V. ,  CHANDRA, Joy ,  KOKER, Altug ,  SURTI, Prasoonkumar ,  PUFFER, David ,  LIAO, Hong Bin ,  RAY, Joydeep ,  APPU, Abhishek R. ,  SHAH, Ankur N. ,  SCHLUESSLER, Travis T. ,  KENNEDY, Jonathan ,  BURKE, Devan

IPC: G06T1/20

公开(公告)号：EP4254203A1

公开(公告)日：2023-10-04

申请号：EP23155456.9

申请日：2023-02-07

Applicant: INTEL Corporation

Inventor： KRISHNAN, Vidhya ,  CHHABRA, Siddhartha ,  PUFFER, David ,  SHAH, Ankur ,  NEMIROFF, Daniel ,  KAKAIYA, Utkarsh

IPC: G06F12/109 ,  G06F12/14 ,  G06F11/10 ,  G06F21/53 ,  G06F21/78

Abstract: Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.

公开(公告)号：EP3385850A1

公开(公告)日：2018-10-10

申请号：EP18165264.5

申请日：2018-03-29

Applicant: INTEL Corporation

Inventor： COORAY, Niranjan L ,  APPU, Abhishek R ,  KOKER, Altug ,  RAY, Joydeep ,  VEMBU, Balaji ,  K, Pattabhiraman ,  PUFFER, David ,  COWPERTHWAITE, David J. ,  SANKARAN, Rajesh M. ,  SINGH, Satyeshwar ,  KP, Sameer ,  SHAH, Ankur N. ,  TIAN, Kun

IPC: G06F12/1027 ,  G06F12/1036 ,  G06F12/1009

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：EP4109283A1

公开(公告)日：2022-12-28

申请号：EP22189858.8

申请日：2018-03-29

Applicant: INTEL Corporation

Inventor： COORAY, Niranjan L ,  APPU, Abhishek R ,  KOKER, Altug ,  RAY, Joydeep ,  VEMBU, Balaji ,  K, Pattabhiraman ,  PUFFER, David ,  COWPERTHWAITE, David J ,  SANKARAN, Rajesh M. ,  SINGH, Satyeshwar ,  KP, Sameer ,  SHAH, Ankur N. ,  TIAN, Kun

IPC: G06F12/1027 ,  G06F12/1036 ,  G06F12/1009 ,  G06F12/1081 ,  G06F13/16 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：EP3809266A1

公开(公告)日：2021-04-21

申请号：EP20213160.3

申请日：2018-03-23

Applicant: INTEL Corporation

Inventor： APPU, Abhishek ,  KOKER, Altug ,  VEMBU, Balaji ,  RAY, Joydeep ,  SINHA, Kamal ,  SURTI, Prasoonkumar ,  VEERNAPU, Kiran C. ,  MAIYURAN, Subramaniam ,  JAHAGIRDAR, Sanjeev S. ,  ASPERHEIM, Eric J. ,  LUEH, Guei-Yuan ,  PUFFER, David ,  FU, Wenyin ,  KABURLASOS, Nikos ,  BOROLE, Bhushan M. ,  MASTRONARDE, Josh B. ,  HURD, Linda L. ,  SCHLUESSLER, Travis T. ,  JANCZAK, Tomasz ,  VENKATESH, Abhishek ,  XIAO, Kai ,  GRAJEWSKI, Slawomir

IPC: G06F9/50

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.