公开(公告)号：EP4485212A1

公开(公告)日：2025-01-01

申请号：EP23215552.3

申请日：2023-12-11

Applicant: Intel Corporation

Inventor： Strong, Beeman ,  Bratanov, Stanislav ,  Metzger, Markus ,  Brandt, Jason W. ,  Jeyasingh, Stalinselvaraj

IPC: G06F11/30 ,  G06F11/34 ,  G06F11/36

Abstract: Apparatus and method for a processor trace trigger tracing. A processor, comprising: a plurality of processing cores configurable as a plurality of logical processors; processor trace circuitry to perform trace operations to capture and process information related to program code executed by one or more of the logical processors; a debug unit to perform debug operations and collect debug data related to execution of the program code; a performance monitoring unit (PMU) comprising a plurality of counter registers, the PMU to collect performance data related to execution of the program code; and a plurality of trigger units, each trigger unit associated with a logical processor of the plurality of logical processors and configured to communicate trigger event data to the processor trace circuitry in response to trigger events received from at least one of the debug unit and the PMU in accordance with values of configuration bits in a corresponding trigger unit configuration register.

公开(公告)号：EP4254197A1

公开(公告)日：2023-10-04

申请号：EP23156438.6

申请日：2023-02-14

Applicant: INTEL Corporation

Inventor： Merten, Matthew ,  Strong, Beeman ,  Cohen, Moshe ,  Yasin, Ahmad ,  Kleen, Andreas ,  Bratanov, Stanislav ,  Gopalakrishnan, Karthik ,  Schmid, Angela ,  Zhou, Grant

IPC: G06F11/30 ,  G06F11/34 ,  G06F11/36

Abstract: Techniques and mechanisms for configuring processor event-based sampling (PEBS) with a set of control registers. In an embodiment, a first control register of a processor is programmed to store a physical address of a location in a buffer which receives PEBS records. The first control register is further programmed or otherwise configured to store an indication of a size of the buffer. A second control register of the processor stores a physical address of a location in the buffer were a next PEBS record is to be stored. In another embodiment, the processor further comprises multiple control registers which variously configure PEBS generation on a per-counter basis.