公开(公告)号：EP4167278A3

公开(公告)日：2023-06-28

申请号：EP22197135.1

申请日：2022-09-22

申请人： INTEL Corporation

发明人： MANEPALLI, Rahul N. ,  EITAN, Amram ,  Arana, Leonel ,  XU, Dingying ,  LIU, Changhua ,  CHO, Steve ,  FENG, Hongxia ,  HAN, Jung Kyu ,  GUO, Xiaoying ,  MC ELHINNY, Kyle

IPC分类号： H01L23/485 ,  H01L23/538 ,  H01L21/60 ,  H01L21/603

摘要： Example methods and apparatuses reduce the likelihood of defects forming in bumps (114, 116, 118, 808, 810) associated with first level interconnects between semiconductor dies (106, 108, 802) and substrates (package substrates (110, 804) or other dies) associated with shifting in plated tin (1802, 2506) upon stripping and swelling of a dry film resist (1002, 1102, 2406), wicking of tin (1802, 2506) upon tin (solder) reflow following removal of the dry film resist (1002, 1102, 2406) (which both could lead to unintended bridging of bumps) and a lack of co-planarity across different bumps due to warpage and/or other factors, by fabricating dummy bumps (702, 812) adjacent operational bridge bumps (604, 810), fabricating bumps (1806+1808+1802) with bases (1806+1808) with non-circular shapes (e.g., polygonal shapes such as octagonal or hexagonal, wherein the shape may correspond to a packing geometry of the bumps), and/or fabricating bumps (2502+2504+2506) with diameters or widths and heights that differ spatially across the area (e.g., between ring-shaped regions (2712)) over which the bumps (2502+2504+2506) are distributed. Such potential defects are reduced in a manner that enables the bumps to be fabricated with a smaller size and/or smaller spacing to meet the ongoing needs of scaling down the overall size of electronic components. In an embodiment, the bumps (114) of the first level interconnects include two different types of bumps corresponding to core bumps (116, 808) (i.e., bumps on the dies (106, 108, 802) through which electrical signals pass between the dies (106, 108, 802) and the package substrate (110, 804) and then to components external to the IC package (100)) and bridge bumps (118, 810) (i.e., bumps on the dies (106, 108, 802) through which electrical signals pass between different ones of the dies (106, 108, 802) within the package (100), via an interconnect bridge (126) embedded in the package substrate (110)), wherein the core bumps (116, 808) are typically larger than the bridge bumps (118, 810). An array of dummy bridge bumps (702, 812) may be positioned adjacent the outer edge or perimeter of the operational bridge bumps (604, 810) so as to at least partially fill in open spaces (608) adjacent an outer edge or perimeter of the array of operational bridge bumps (604, 810) and thus limit bump shifting upon resist swelling in the remaining open space to the dummy bridge bumps (702, 812), thereby protecting the operational bridge bumps (604, 810), as well as to improve plating uniformity (e.g., the relative bump thickness variation (rBTV)) across the operational bridge bumps (604, 810). The operational bridge bumps (604, 810) and the dummy bridge bumps (702, 812) may have the same or different size and shape. The dummy bridge bumps (812) may have a shorter height so that they do not form a connection that extends a full distance between the die (802) and the package substrate (804).

公开(公告)号：EP4254484A1

公开(公告)日：2023-10-04

申请号：EP23156628.2

申请日：2023-02-14

申请人： INTEL Corporation

发明人： ARRINGTON, Kyle ,  Liu, Kuang C. ,  SHAN, Bohan ,  FENG, Hongxia ,  JOSEPHSON, Don Douglas ,  MOREIN, Stephen ,  RADHAKRISHNAN, Kaladhar

IPC分类号： H01L23/14 ,  H01L23/50 ,  H01L25/065 ,  H01L23/367

摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die on the package substrate. In an embodiment, the electronic package further comprises a voltage regulator on the package substrate adjacent to the die, and a metal printed circuit board (PCB) heat spreader. In an embodiment, a trace on the metal PCB heat spreader couples the die to the voltage regulator.

公开(公告)号：EP4184569A3

公开(公告)日：2023-08-09

申请号：EP22201685.9

申请日：2022-10-14

申请人： INTEL Corporation

发明人： SHAN, Bohan ,  CHEN, Haobo ,  KARHADE, Omkar ,  SANKARASUBRAMANIAN, Malavarayan ,  XU, Dingying ,  DUAN, Gang ,  NIE, Bai ,  GUO, Xiaoying ,  DARMAWIKARTA, Kristof ,  FENG, Hongxia ,  PIETAMBARAM, Srinivas V. ,  ECTON, Jeremy

IPC分类号： H01L23/485 ,  H01L21/603 ,  H01L25/065 ,  H05K3/34

摘要： In a microelectronic package, one or more solder joints (130A-B, 206A-D, 226, 640) between two substrates (102, 104, 202A, 202B, 204, 224, 228, 600, 630) are formed as full IMC (intermetallic compound) solder joints, while other solder joints (132, 210, 220, 642) may be formed as regular solder joints. The full IMC solder joint (130A-B, 206A-D, 226, 640) includes a continuous layer (e.g., from a top pad (124, 128, 636) to a bottom pad (122, 126, 606)) of intermetallic compounds and may include copper particles (302) throughout the full IMC solder joints (130A-B, 206A-D, 226, 640). The full IMC solder joint (130A-B, 206A-D, 226, 640) may include cured epoxy from a no-remelt solder around the continuous layer of IMCs. The full IMC solder joint (130A-B, 206A-D, 226, 640) has a melting point that is higher than that of the regular solder joints (132, 210, 220, 642). The full IMC solder joint (130A-B, 206A-D, 226, 640) may be between dummy pads (126, 128, 606, 636) on the first and second substrates (102, 104, 600, 630) or may include an interconnect for power delivery between the first substrate (102, 600) and the second substrate (104, 630) or an input/output (I/O) interconnect between the first substrate (102, 600) and the second substrate (104, 630). The first substrate (102, 204, 224, 600) and the second substrate (104, 202A, 202B, 228, 630) may include one or more of: a substrate, a die, a bridge die, an interposer, a patch, a thin film, a motherboard, a redistribution layer (RDL), and an organic PCB, in particular, the first substrate (204) may be a core substrate and the second substrate (202A, 202B) may be a substrate patch, or the full IMC solder joint (226) may be located in a via (222) in the first substrate (224), wherein the second substrate may be a bridge die (228). The solder joints (130A-B, 206A-D, 226, 640) may include at least three full IMC solder joints, wherein the number of full IMC solder joints is in a range of one solder joint to 50% of all solder joints. In a method of manufacturing the microelectronic package, regular solder (602) is dispensed on a plurality of conductive contacts (604) of a first substrate (600), no-remelt solder (620) is dispensed on another conductive contact (606) of the first substrate (600), and a second substrate (630) is bonded to the first substrate (600), forming the full IMC solder joint (640) from the no-remelt solder (620). The no-remelt solder (620) may be a TLPS (transient liquid phase sintering) paste, e.g., a solder paste that includes copper (Cu) particles together with tin (Sn) or tin alloy (such as Sn-Bi) particles dispersed in a flux system, such as an epoxy flux. The no-remelt solder (620) may have a higher melting point than the regular solder (602). The location of the full IMC solder joints (130A-B, 206A-D, 226, 640) may be selected to maximize mechanical stability both during downstream reflow (eliminating die or substrate movement, during multiple thermal processing steps (e.g., reflow steps) while forming hierarchical interconnections) and of the final package. For example, the full IMC joints (130A-B, 206A-D, 226, 640) may be formed in areas other than corners to prevent cracking. The full IMC (130A-B, 206A-D, 226, 640) joints may also be distributed (e.g., distributed uniformly) amongst the regular solder joints to increase stability during assembly in all areas between the substrates.

公开(公告)号：EP4184569A2

公开(公告)日：2023-05-24

申请号：EP22201685.9

申请日：2022-10-14

申请人： INTEL Corporation

发明人： SHAN, Bohan ,  CHEN, Haobo ,  KARHADE, Omkar ,  SANKARASUBRAMANIAN, Malavarayan ,  XU, Dingying ,  DUAN, Gang ,  NIE, Bai ,  GUO, Xiaoying ,  DARMAWIKARTA, Kristof ,  FENG, Hongxia ,  PIETAMBARAM, Srinivas V. ,  ECTON, Jeremy

IPC分类号： H01L23/485 ,  H01L21/603 ,  H01L25/065 ,  H05K3/34

摘要： In a microelectronic package, one or more solder joints (130A-B, 206A-D, 226, 640) between two substrates (102, 104, 202A, 202B, 204, 224, 228, 600, 630) are formed as full IMC (intermetallic compound) solder joints, while other solder joints (132, 210, 220, 642) may be formed as regular solder joints. The full IMC solder joint (130A-B, 206A-D, 226, 640) includes a continuous layer (e.g., from a top pad (124, 128, 636) to a bottom pad (122, 126, 606)) of intermetallic compounds and may include copper particles (302) throughout the full IMC solder joints (130A-B, 206A-D, 226, 640). The full IMC solder joint (130A-B, 206A-D, 226, 640) may include cured epoxy from a no-remelt solder around the continuous layer of IMCs. The full IMC solder joint (130A-B, 206A-D, 226, 640) has a melting point that is higher than that of the regular solder joints (132, 210, 220, 642). The full IMC solder joint (130A-B, 206A-D, 226, 640) may be between dummy pads (126, 128, 606, 636) on the first and second substrates (102, 104, 600, 630) or may include an interconnect for power delivery between the first substrate (102, 600) and the second substrate (104, 630) or an input/output (I/O) interconnect between the first substrate (102, 600) and the second substrate (104, 630). The first substrate (102, 204, 224, 600) and the second substrate (104, 202A, 202B, 228, 630) may include one or more of: a substrate, a die, a bridge die, an interposer, a patch, a thin film, a motherboard, a redistribution layer (RDL), and an organic PCB, in particular, the first substrate (204) may be a core substrate and the second substrate (202A, 202B) may be a substrate patch, or the full IMC solder joint (226) may be located in a via (222) in the first substrate (224), wherein the second substrate may be a bridge die (228). The solder joints (130A-B, 206A-D, 226, 640) may include at least three full IMC solder joints, wherein the number of full IMC solder joints is in a range of one solder joint to 50% of all solder joints. In a method of manufacturing the microelectronic package, regular solder (602) is dispensed on a plurality of conductive contacts (604) of a first substrate (600), no-remelt solder (620) is dispensed on another conductive contact (606) of the first substrate (600), and a second substrate (630) is bonded to the first substrate (600), forming the full IMC solder joint (640) from the no-remelt solder (620). The no-remelt solder (620) may be a TLPS (transient liquid phase sintering) paste, e.g., a solder paste that includes copper (Cu) particles together with tin (Sn) or tin alloy (such as Sn-Bi) particles dispersed in a flux system, such as an epoxy flux. The no-remelt solder (620) may have a higher melting point than the regular solder (602). The location of the full IMC solder joints (130A-B, 206A-D, 226, 640) may be selected to maximize mechanical stability both during downstream reflow (eliminating die or substrate movement, during multiple thermal processing steps (e.g., reflow steps) while forming hierarchical interconnections) and of the final package. For example, the full IMC joints (130A-B, 206A-D, 226, 640) may be formed in areas other than corners to prevent cracking. The full IMC (130A-B, 206A-D, 226, 640) joints may also be distributed (e.g., distributed uniformly) amongst the regular solder joints to increase stability during assembly in all areas between the substrates.

公开(公告)号：EP4167278A2

公开(公告)日：2023-04-19

申请号：EP22197135.1

申请日：2022-09-22

申请人： INTEL Corporation

发明人： MANEPALLI, Rahul N. ,  EITAN, Amram ,  Arana, Leonel ,  XU, Dingying ,  LIU, Changhua ,  CHO, Steve ,  FENG, Hongxia ,  HAN, Jung Kyu ,  GUO, Xiaoying ,  MC ELHINNY, Kyle

IPC分类号： H01L23/485 ,  H01L23/538 ,  H01L21/60 ,  H01L21/603

摘要： Example methods and apparatuses reduce the likelihood of defects forming in bumps (114, 116, 118, 808, 810) associated with first level interconnects between semiconductor dies (106, 108, 802) and substrates (package substrates (110, 804) or other dies) associated with shifting in plated tin (1802, 2506) upon stripping and swelling of a dry film resist (1002, 1102, 2406), wicking of tin (1802, 2506) upon tin (solder) reflow following removal of the dry film resist (1002, 1102, 2406) (which both could lead to unintended bridging of bumps) and a lack of co-planarity across different bumps due to warpage and/or other factors, by fabricating dummy bumps (702, 812) adjacent operational bridge bumps (604, 810), fabricating bumps (1806+1808+1802) with bases (1806+1808) with non-circular shapes (e.g., polygonal shapes such as octagonal or hexagonal, wherein the shape may correspond to a packing geometry of the bumps), and/or fabricating bumps (2502+2504+2506) with diameters or widths and heights that differ spatially across the area (e.g., between ring-shaped regions (2712)) over which the bumps (2502+2504+2506) are distributed. Such potential defects are reduced in a manner that enables the bumps to be fabricated with a smaller size and/or smaller spacing to meet the ongoing needs of scaling down the overall size of electronic components. In an embodiment, the bumps (114) of the first level interconnects include two different types of bumps corresponding to core bumps (116, 808) (i.e., bumps on the dies (106, 108, 802) through which electrical signals pass between the dies (106, 108, 802) and the package substrate (110, 804) and then to components external to the IC package (100)) and bridge bumps (118, 810) (i.e., bumps on the dies (106, 108, 802) through which electrical signals pass between different ones of the dies (106, 108, 802) within the package (100), via an interconnect bridge (126) embedded in the package substrate (110)), wherein the core bumps (116, 808) are typically larger than the bridge bumps (118, 810). An array of dummy bridge bumps (702, 812) may be positioned adjacent the outer edge or perimeter of the operational bridge bumps (604, 810) so as to at least partially fill in open spaces (608) adjacent an outer edge or perimeter of the array of operational bridge bumps (604, 810) and thus limit bump shifting upon resist swelling in the remaining open space to the dummy bridge bumps (702, 812), thereby protecting the operational bridge bumps (604, 810), as well as to improve plating uniformity (e.g., the relative bump thickness variation (rBTV)) across the operational bridge bumps (604, 810). The operational bridge bumps (604, 810) and the dummy bridge bumps (702, 812) may have the same or different size and shape. The dummy bridge bumps (812) may have a shorter height so that they do not form a connection that extends a full distance between the die (802) and the package substrate (804).