公开(公告)号：EP3716320A1

公开(公告)日：2020-09-30

申请号：EP20156743.5

申请日：2020-02-11

申请人： INTEL Corporation

发明人： PIETAMBARAM, Srinivas V. ,  IBRAHIM, Tarek ,  DARMAWIKARTA, Kristof ,  MANEPALLI, Rahul N. ,  MALLIK, Debendra ,  SANKMAN, Robert L

IPC分类号： H01L23/15 ,  H01L23/538

摘要： A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

公开(公告)号：EP4270072A1

公开(公告)日：2023-11-01

申请号：EP23157645.5

申请日：2023-02-20

申请人： INTEL Corporation

发明人： TANAKA, Hiroki ,  NIE, Bai ,  DARMAWIKARTA, Kristof ,  MAHALINGAM, Hari

IPC分类号： G02B6/12 ,  G02B6/136

摘要： Techniques for signal amplification for a photonic integrated circuit (PIC) die are disclosed. In the illustrative embodiment, an optical fiber (104) is coupled to an input signal waveguide (110) in a glass interposer (102), and an input signal waveguide (130) of a PIC die is coupled to the input signal waveguide (110) of the glass interposer (102). In order to compensate for any coupling losses, the input signal waveguide (110) of the glass interposer (102) is active, amplifying an input signal. Light in a pump waveguide (114) near the input signal waveguide (110) pumps ions in the input signal waveguide (110) into a population inversion, allowing them to amplify the input signal.

公开(公告)号：EP4184569A2

公开(公告)日：2023-05-24

申请号：EP22201685.9

申请日：2022-10-14

申请人： INTEL Corporation

发明人： SHAN, Bohan ,  CHEN, Haobo ,  KARHADE, Omkar ,  SANKARASUBRAMANIAN, Malavarayan ,  XU, Dingying ,  DUAN, Gang ,  NIE, Bai ,  GUO, Xiaoying ,  DARMAWIKARTA, Kristof ,  FENG, Hongxia ,  PIETAMBARAM, Srinivas V. ,  ECTON, Jeremy

IPC分类号： H01L23/485 ,  H01L21/603 ,  H01L25/065 ,  H05K3/34

摘要： In a microelectronic package, one or more solder joints (130A-B, 206A-D, 226, 640) between two substrates (102, 104, 202A, 202B, 204, 224, 228, 600, 630) are formed as full IMC (intermetallic compound) solder joints, while other solder joints (132, 210, 220, 642) may be formed as regular solder joints. The full IMC solder joint (130A-B, 206A-D, 226, 640) includes a continuous layer (e.g., from a top pad (124, 128, 636) to a bottom pad (122, 126, 606)) of intermetallic compounds and may include copper particles (302) throughout the full IMC solder joints (130A-B, 206A-D, 226, 640). The full IMC solder joint (130A-B, 206A-D, 226, 640) may include cured epoxy from a no-remelt solder around the continuous layer of IMCs. The full IMC solder joint (130A-B, 206A-D, 226, 640) has a melting point that is higher than that of the regular solder joints (132, 210, 220, 642). The full IMC solder joint (130A-B, 206A-D, 226, 640) may be between dummy pads (126, 128, 606, 636) on the first and second substrates (102, 104, 600, 630) or may include an interconnect for power delivery between the first substrate (102, 600) and the second substrate (104, 630) or an input/output (I/O) interconnect between the first substrate (102, 600) and the second substrate (104, 630). The first substrate (102, 204, 224, 600) and the second substrate (104, 202A, 202B, 228, 630) may include one or more of: a substrate, a die, a bridge die, an interposer, a patch, a thin film, a motherboard, a redistribution layer (RDL), and an organic PCB, in particular, the first substrate (204) may be a core substrate and the second substrate (202A, 202B) may be a substrate patch, or the full IMC solder joint (226) may be located in a via (222) in the first substrate (224), wherein the second substrate may be a bridge die (228). The solder joints (130A-B, 206A-D, 226, 640) may include at least three full IMC solder joints, wherein the number of full IMC solder joints is in a range of one solder joint to 50% of all solder joints. In a method of manufacturing the microelectronic package, regular solder (602) is dispensed on a plurality of conductive contacts (604) of a first substrate (600), no-remelt solder (620) is dispensed on another conductive contact (606) of the first substrate (600), and a second substrate (630) is bonded to the first substrate (600), forming the full IMC solder joint (640) from the no-remelt solder (620). The no-remelt solder (620) may be a TLPS (transient liquid phase sintering) paste, e.g., a solder paste that includes copper (Cu) particles together with tin (Sn) or tin alloy (such as Sn-Bi) particles dispersed in a flux system, such as an epoxy flux. The no-remelt solder (620) may have a higher melting point than the regular solder (602). The location of the full IMC solder joints (130A-B, 206A-D, 226, 640) may be selected to maximize mechanical stability both during downstream reflow (eliminating die or substrate movement, during multiple thermal processing steps (e.g., reflow steps) while forming hierarchical interconnections) and of the final package. For example, the full IMC joints (130A-B, 206A-D, 226, 640) may be formed in areas other than corners to prevent cracking. The full IMC (130A-B, 206A-D, 226, 640) joints may also be distributed (e.g., distributed uniformly) amongst the regular solder joints to increase stability during assembly in all areas between the substrates.

公开(公告)号：EP3732718A1

公开(公告)日：2020-11-04

申请号：EP17936282.7

申请日：2017-12-29

申请人： INTEL Corporation

发明人： PIETAMBARAM, Srinivas ,  MAY, Robert Alan ,  DARMAWIKARTA, Kristof ,  TANAKA, Hiroki ,  MANEPALLI, Rahul N. ,  BOYAPATI, Sri Ranga Sai

IPC分类号： H01L25/07 ,  H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/485

公开(公告)号：EP4248249A1

公开(公告)日：2023-09-27

申请号：EP21895299.2

申请日：2021-09-09

申请人： INTEL Corporation

发明人： PIETAMBARAM, Srinivas V. ,  MARIN, Brandon C. ,  PAITAL, Sameer ,  VADLIMANI, Sai ,  MANEPALLI, Rahul N. ,  LI, Xiaoqian ,  POTHUKUCHI, Suresh V. ,  SHARAN, Sujit ,  SARKAR, Arnab ,  KARHADE, Omkar ,  DESHPANDE, Nitin ,  PRATAP, Divya ,  ECTON, Jeremy ,  MALLIK, Debendra ,  MAHAJAN, Ravindranath V. ,  ZHANG, Zhichao ,  AYGÜN, Kemal ,  NIE, Bai ,  DARMAWIKARTA, Kristof ,  JAUSSI, James E. ,  GAMBA, Jason M. ,  CASPER, Bryan K. ,  DUAN, Gang ,  INTI, Rajesh ,  MANSURI, Mozhgan ,  JADHAV, Susheel ,  BROWN, Kenneth ,  AGRAWAL, Ankar ,  DOBRIYAL, Priyanka

IPC分类号： G02B6/42 ,  H01L31/0203 ,  H01L23/538 ,  H01L25/16

公开(公告)号：EP4156254A1

公开(公告)日：2023-03-29

申请号：EP22183759.4

申请日：2022-07-08

申请人： Intel Corporation

发明人： ECTON, Jeremy ,  DARMAWIKARTA, Kristof ,  NAD, Suddhasattwa ,  OJEDA, Oscar ,  NIE, Bai ,  MARIN, Brandon ,  DUAN, Gang ,  VEHONSKY, Jacob ,  OZKAN, Onur ,  HAEHN, Nicholas

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L21/48

摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

公开(公告)号：EP3462484A1

公开(公告)日：2019-04-03

申请号：EP18190102.6

申请日：2018-08-21

申请人： INTEL Corporation

发明人： ALEKSOV, Aleksandar ,  SARKAR, Arnab ,  SAIN, Arghya ,  DARMAWIKARTA, Kristof ,  BRAUNISCH, Henning ,  PARMAR, Prashant D. ,  SHARAN, Sujit ,  SWAN, Johanna M. ,  EID, Feras

IPC分类号： H01L23/522 ,  G06F17/50 ,  H01L23/528 ,  H01L23/66 ,  H05K1/02

摘要： Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.

公开(公告)号：EP4341991A1

公开(公告)日：2024-03-27

申请号：EP22805131.4

申请日：2022-03-30

申请人： INTEL Corporation

发明人： DUONG, Benjamin ,  GAAN, Sandeep ,  PIETAMBARAM, Srinivas ,  LI, Wenchao ,  DARMAWIKARTA, Kristof ,  AGRAWAL, Ankur ,  MAHAJAN, Ravindranath

IPC分类号： H01L23/00 ,  H01L25/18 ,  H01L25/065

公开(公告)号：EP4302579A1

公开(公告)日：2024-01-10

申请号：EP22763731.1

申请日：2022-02-02

申请人： INTEL Corporation

发明人： PIETAMBARAM, Srinivas ,  TADAYON, Pooya ,  DARMAWIKARTA, Kristof ,  IBRAHIM, Tarek ,  CHATTERJEE, Prithwish

IPC分类号： H05K1/02 ,  H01L23/64 ,  H01L49/02

公开(公告)号：EP4102556A1

公开(公告)日：2022-12-14

申请号：EP22177322.9

申请日：2022-06-03

申请人： INTEL Corporation

发明人： DARMAWIKARTA, Kristof ,  DUONG, Benjamin ,  PIETAMBARAM, Srinivas V. ,  SOUNART, Thomas ,  ALEKSOV, Aleksandar ,  ELSHERBINI, Adel A.

IPC分类号： H01L23/498 ,  H01G4/01 ,  H01G4/30 ,  H01G4/33

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die in a first dielectric layer; and a capacitor including a first conductive pillar and a second conductive pillar in the first dielectric layer, each pillar having a first end and an opposing second end, where the first and second conductive pillars form a first plate of the capacitor; a second dielectric layer on the die and on the second end of the first and second conductive pillars extending at least partially along a first thickness of the first and second conductive pillars and tapering from the second end towards the first end; and a metal layer on the second dielectric layer, wherein the metal layer extends at least partially along a second thickness of the first and second conductive pillars, where the metal layer forms a second plate of the capacitor.