公开(公告)号：EP4033352A1

公开(公告)日：2022-07-27

申请号：EP22161283.1

申请日：2020-02-07

申请人： INTEL Corporation

发明人： Shemy, Regev ,  Sperber, Zeev ,  Feghali, Wajdi ,  Gopal, Vinodh ,  Gradstein, Amit ,  Rubanovich, Simon ,  Gulley, Sean ,  Albrekht, Ilya ,  Doweck, Jacob ,  Yallouz, Jose ,  Anati, Ittai

IPC分类号： G06F9/30

摘要： Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor comprises a decode circuit to decode a first instruction and an execution circuit coupled with the decode circuit. The first instruction comprises a plurality of fields to specify a first vector register and a second vector register, the first vector register to store a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register to store a fifth 64-bit data element and a sixth 64-bit data element. The execution circuit is to perform operations corresponding to the first instruction, including to: generate a result and store the result in the first vector register. The result is to include: a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by nineteen bits exclusive OR'd (XOR'd) with the fifth 64-bit data element rotated right by sixty-one bits XOR'd with the fifth 64-bit data element shifted right by six bits; a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the sixth 64-bit data element rotated right by nineteen bits XOR'd with the sixth 64-bit data element rotated right by sixty-one bits XOR'd with the sixth 64-bit data element shifted right by six bits; a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the first 64-bit result element rotated right by nineteen bits XOR'd with the first 64-bit result element rotated right by sixty-one bits XOR'd with the first 64-bit result element shifted right by six bits; and a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the second 64-bit result element rotated right by nineteen bits XOR'd with the second 64-bit result element rotated right by sixty-one bits XOR'd with the second 64-bit result element shifted right by six bits; and.

公开(公告)号：EP4016291A1

公开(公告)日：2022-06-22

申请号：EP22156135.0

申请日：2020-02-07

申请人： Intel Corporation

发明人： Shemy, Regev ,  Sperber, Zeev ,  Feghali, Wajdi ,  Gopal, Vinodh ,  Gradstein, Amit ,  Rubanovich, Simon ,  Gulley, Sean ,  Albrekht, Ilya ,  Doweck, Jacob ,  Yallouz, Jose ,  Anati, Ittai

IPC分类号： G06F9/30

摘要： Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor comprises a decode circuit to decode a first instruction, the first instruction comprising a plurality of fields to specify a first vector register and a second vector register, the first vector register to store a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register to store a fifth 64-bit data element; and an execution circuit coupled with the decode circuit. The execution circuit is to perform operations corresponding to the first instruction, including to: generate a result and store the result in the first vector register. The result is to include: a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the second 64-bit data element rotated right by one bit exclusive OR'd (XOR'd) with the second 64-bit data element rotated right by eight bits XOR'd with the second 64-bit data element shifted right by seven bits; a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the third 64-bit data element rotated right by one bit XOR'd with the third 64-bit data element rotated right by eight bits XOR'd with the third 64-bit data element shifted right by seven bits; a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the fourth 64-bit data element rotated right by one bit XOR'd with the fourth 64-bit data element rotated right by eight bits XOR'd with the fourth 64-bit data element shifted right by seven bits; and a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by one bit XOR'd with the fifth 64-bit data element rotated right by eight bits XOR'd with the fifth 64-bit data element shifted right by seven bits.

公开(公告)号：EP3716049A1

公开(公告)日：2020-09-30

申请号：EP20156066.1

申请日：2020-02-07

申请人： Intel Corporation

发明人： Shemy, Regev ,  Sperber, Zeev ,  Feghali, Wajdi ,  Gopal, Vinodh ,  Gradstein, Amit ,  Rubanovich, Simon ,  Gulley, Sean ,  Albrekht, Ilya ,  Doweck, Jacob ,  Yallouz, Jose ,  Anati, Ittai

IPC分类号： G06F9/30

摘要： Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.