公开(公告)号：EP3671521A1

公开(公告)日：2020-06-24

申请号：EP19203470.0

申请日：2019-10-16

申请人： INTEL Corporation

发明人： Ouziel, Ido ,  Aharon, Arie ,  Caspi, Dror ,  Chaikin, Baruch ,  Doweck, Jacob ,  Gerzon, Gideon ,  Huntley, Barry E. ,  McKeen, Francis X. ,  Neiger, Gilbert ,  Rozas, Carlos V. ,  Sahita, Ravi L. ,  Shanbhogue, Vedvyas ,  Zaltsman, Assaf ,  Khosravi, Hormuzd M.

IPC分类号： G06F21/79 ,  G06F21/60 ,  G06F12/14

摘要： Implementations described provide hardware support for the co-existence of restricted and non-restricted encryption keys on a computing system. Such hardware support may comprise a processor having a core, a hardware register to store a bit range to identify a number of bits, of physical memory addresses, that define key identifiers (IDs) and a partition key ID identifying a boundary between non-restricted and restricted key IDs. The core may allocate at least one of the non-restricted key IDs to a software program, such as a hypervisor. The core may further allocate a restricted key ID to a trust domain whose trust computing base does not comprise the software program. A memory controller coupled to the core may allocate a physical page of a memory to the trust domain, wherein data of the physical page of the memory is to be encrypted with an encryption key associated with the restricted key ID.

公开(公告)号：EP4016291A1

公开(公告)日：2022-06-22

申请号：EP22156135.0

申请日：2020-02-07

申请人： Intel Corporation

发明人： Shemy, Regev ,  Sperber, Zeev ,  Feghali, Wajdi ,  Gopal, Vinodh ,  Gradstein, Amit ,  Rubanovich, Simon ,  Gulley, Sean ,  Albrekht, Ilya ,  Doweck, Jacob ,  Yallouz, Jose ,  Anati, Ittai

IPC分类号： G06F9/30

摘要： Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor comprises a decode circuit to decode a first instruction, the first instruction comprising a plurality of fields to specify a first vector register and a second vector register, the first vector register to store a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register to store a fifth 64-bit data element; and an execution circuit coupled with the decode circuit. The execution circuit is to perform operations corresponding to the first instruction, including to: generate a result and store the result in the first vector register. The result is to include: a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the second 64-bit data element rotated right by one bit exclusive OR'd (XOR'd) with the second 64-bit data element rotated right by eight bits XOR'd with the second 64-bit data element shifted right by seven bits; a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the third 64-bit data element rotated right by one bit XOR'd with the third 64-bit data element rotated right by eight bits XOR'd with the third 64-bit data element shifted right by seven bits; a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the fourth 64-bit data element rotated right by one bit XOR'd with the fourth 64-bit data element rotated right by eight bits XOR'd with the fourth 64-bit data element shifted right by seven bits; and a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by one bit XOR'd with the fifth 64-bit data element rotated right by eight bits XOR'd with the fifth 64-bit data element shifted right by seven bits.

公开(公告)号：EP4033352A1

公开(公告)日：2022-07-27

申请号：EP22161283.1

申请日：2020-02-07

申请人： INTEL Corporation

发明人： Shemy, Regev ,  Sperber, Zeev ,  Feghali, Wajdi ,  Gopal, Vinodh ,  Gradstein, Amit ,  Rubanovich, Simon ,  Gulley, Sean ,  Albrekht, Ilya ,  Doweck, Jacob ,  Yallouz, Jose ,  Anati, Ittai

IPC分类号： G06F9/30

摘要： Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor comprises a decode circuit to decode a first instruction and an execution circuit coupled with the decode circuit. The first instruction comprises a plurality of fields to specify a first vector register and a second vector register, the first vector register to store a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register to store a fifth 64-bit data element and a sixth 64-bit data element. The execution circuit is to perform operations corresponding to the first instruction, including to: generate a result and store the result in the first vector register. The result is to include: a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by nineteen bits exclusive OR'd (XOR'd) with the fifth 64-bit data element rotated right by sixty-one bits XOR'd with the fifth 64-bit data element shifted right by six bits; a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the sixth 64-bit data element rotated right by nineteen bits XOR'd with the sixth 64-bit data element rotated right by sixty-one bits XOR'd with the sixth 64-bit data element shifted right by six bits; a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the first 64-bit result element rotated right by nineteen bits XOR'd with the first 64-bit result element rotated right by sixty-one bits XOR'd with the first 64-bit result element shifted right by six bits; and a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the second 64-bit result element rotated right by nineteen bits XOR'd with the second 64-bit result element rotated right by sixty-one bits XOR'd with the second 64-bit result element shifted right by six bits; and.

公开(公告)号：EP3671474A1

公开(公告)日：2020-06-24

申请号：EP19209897.8

申请日：2019-11-19

申请人： Intel Corporation

发明人： Ouziel, Ido ,  Aharon, Arie ,  Caspi, Dror ,  Chaikin, Baruch ,  Doweck, Jacob ,  Gerzon, Gideon ,  Huntley, Barry E. ,  McKeen, Francis X. ,  Neiger, Gilbert ,  Rozas, Carlos V. ,  Sahita, Ravi L. ,  Shanbhogue, Vedvyas ,  Zaltsman, Assaf

IPC分类号： G06F12/14 ,  G06F21/12 ,  G06F21/60 ,  G06F21/62 ,  G06F21/72 ,  G06F9/455 ,  G06F21/53

摘要： A processor includes a processor core. A register of the core is to store:
a bit range for a number of address bits of physical memory addresses used for key identifiers (IDs), and a first key ID to identify a boundary between non-restricted key IDs and restricted key IDs of the key identifiers. A memory controller is to: determine, via access to bit range and the first key ID in the register, a key ID range of the restricted key IDs within the physical memory addresses; access a processor state that a first logical processor of the processor core executes in an untrusted domain mode; receive a memory transaction, from the first logical processor, including an address associated with a second key ID; and generate a fault in response to a determination that the second key ID is within a key ID range of the restricted key IDs.

公开(公告)号：EP4432104A1

公开(公告)日：2024-09-18

申请号：EP23214261.2

申请日：2023-12-05

申请人： INTEL Corporation

发明人： Brandt, Jason ,  Ouziel, Ido ,  Chynoweth, Michael ,  Rivas Toledano, Raoul ,  Neiger, Gilbert ,  Kleen, Andreas ,  Doweck, Jacob ,  Nelson, Andrew

IPC分类号： G06F12/1027

CPC分类号： G06F12/1027 ,  G06F2212/68220130101 ,  G06F2212/68320130101

摘要： An apparatus and method are described for reduced power TLB management. For example, one embodiment of a processor comprises: a plurality of cores; a first core of the plurality of cores comprising: a first translation lookaside buffer (TLB) to store address translations associated with page table walk operations, and power management logic to cause the first core to enter into a first low power state in which the address translations in the first TLB are no longer valid, wherein prior to entering into the low power state, the first core is to write an indication in a memory location that the first TLB no longer contains valid address translations; a second core of the plurality of cores to perform an operation requiring invalidation of one or more of the address translations previously stored in the first TLB, the second core to determine whether to transmit a request to the first core to invalidate the one or more address translations based on the indication.

公开(公告)号：EP3716049A1

公开(公告)日：2020-09-30

申请号：EP20156066.1

申请日：2020-02-07

申请人： Intel Corporation

发明人： Shemy, Regev ,  Sperber, Zeev ,  Feghali, Wajdi ,  Gopal, Vinodh ,  Gradstein, Amit ,  Rubanovich, Simon ,  Gulley, Sean ,  Albrekht, Ilya ,  Doweck, Jacob ,  Yallouz, Jose ,  Anati, Ittai

IPC分类号： G06F9/30

摘要： Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.