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公开(公告)号：EP4109278A1
公开(公告)日：2022-12-28
申请号：EP22159362.7
申请日：2022-03-01
申请人： Intel Corporation
摘要： An integrated circuit includes a compression accelerator to process a request from software to compress source data into an output file. The compression accelerator includes early-abort circuitry to provide for early abort of compression operations. In particular, the compression accelerator uses a predetermined sample size to compute an estimated size for a portion of the output file. The sample size specifies how much of the source data is to be analyzed before computing the estimated size. The compression accelerator also determines whether the estimated size reflects an acceptable amount of compression, based on a predetermined early-abort threshold. The compression accelerator aborts the request if the estimated size does not reflect the acceptable amount of compression. The compression accelerator may complete the request if the estimated size reflects the acceptable amount of compression. Other embodiments are described and claimed.
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公开(公告)号：EP4020232A1
公开(公告)日：2022-06-29
申请号：EP21198863.9
申请日：2021-09-24
申请人： Intel Corporation
IPC分类号： G06F12/1009 , G06F12/08 , G06F12/0882 , G06F12/0886 , G06F12/04
摘要： An embodiment of an integrated circuit may comprise, coupled to a core, hardware decompression accelerators, a compressed cache, a processor communicatively coupled to the hardware decompression accelerators and the compressed cache, and memory communicatively coupled to the processor, wherein the memory stores microcode instructions that when executed by the processor causes the processor to load a page table entry in response to an indication of a page fault, determine if the page table entry indicates that the page is to be decompressed on fault, and, if so determined, modify a first decompression work descriptor at a first address and a second decompression work descriptor at a second address based on information from the page table entry, and generate a first enqueue transaction to the hardware decompression accelerators with the first address of the first decompression work descriptor and a second enqueue transaction to the hardware decompression accelerators with the second address of the second decompression work descriptor. Other embodiments are disclosed and claimed.
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3.发明公开Flexible Architecture and Instruction for Advanced Encryption Standard (AES) 审中-公开灵活的建筑物和安全防护装备Verschlüsselungs标准
公开(公告)号：EP2852088A1
公开(公告)日：2015-03-25
申请号：EP14169143.6
申请日：2008-03-25
申请人： Intel Corporation
发明人： Gueron, Shay , Feghali, Wajdi , Gopal, Vinodh , Raghunandan, Makaram , Dixon, Martin , Chennupaty, Srinivas , Kounavis, Michael
CPC分类号： H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
摘要： Methods and devices for use with the advanced encryption standard (AES) are presented including a processor comprising a decode unit to decode a single round encryption instruction to perform an AES single round encryption operation, wherein the single round encryption instruction specifies a destination register to store 128-bit input data and a source register to store a 128-bit round key; and an execution unit to execute micro-operations based on the single round encryption instruction, wherein the execution unit is to receive the 128-bit input data and the 128-bit round key, and wherein the execution unit is to perform the AES single round encryption operation on the 128-bit input data using the round key and to store 128-bit result data in the destination register.
摘要翻译： 提供了与高级加密标准（AES）一起使用的方法和装置，包括：处理器，包括解码单元，用于解码单循环加密指令以执行AES单循环加密操作，其中单轮加密指令指定目的地寄存器以存储 128位输入数据和源寄存器，用于存储128位圆键; 以及执行单元，用于基于所述单轮加密指令执行微操作，其中所述执行单元将接收所述128位输入数据和所述128位循环密钥，并且其中所述执行单元执行所述AES单回合 使用循环密钥对128位输入数据进行加密操作，并将128位结果数据存储在目标寄存器中。
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公开(公告)号：EP4152147A1
公开(公告)日：2023-03-22
申请号：EP22188194.9
申请日：2022-08-02
申请人： Intel Corporation
发明人： Boemer, Fabian , Gopal, Vinodh , Seifu, Gelila , Kim, Sejun , Crawford, Jack
IPC分类号： G06F9/30
摘要： One embodiment provides a processor comprising first circuitry to decode an instruction into a decoded instruction, the instruction to indicate a first source operand and a second source operand and second circuitry including a processing resource to execute the decoded instruction, wherein responsive to the decoded instruction, the processing resource is to output a result of first source operand data minus second source operand data in response to a determination by the processing resource that the first source operand data is greater than or equal to the second source operand data, otherwise the processing resource is to output the first source operand data.
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5.发明公开
公开(公告)号：EP4020817A1
公开(公告)日：2022-06-29
申请号：EP21197976.0
申请日：2021-09-21
申请人： INTEL Corporation
发明人： Guilford, James , Gopal, Vinodh , Cutter, Daniel , Yap, Kirk
摘要： Apparatus and method for efficient compression block decoding using content-addressable structure for header processing. For example, one embodiment of an apparatus comprises: a header parser to extract a sequence of tokens and corresponding length values from a header of a compression block, the tokens and corresponding length values associated with a type of compression used to compress a payload of the compression block; and a content-addressable data structure builder to construct a content-addressable data structure based on the tokens and length values, the content-addressable data structure builder to write an entry in the content-addressable data structure comprising a length value and a count value, the count value indicating a number of times the length value was previously written to an entry in the content-addressable data structure.
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公开(公告)号：EP4016848A1
公开(公告)日：2022-06-22
申请号：EP21194682.7
申请日：2021-09-03
申请人： INTEL Corporation
发明人： Guilford, James , Gopal, Vinodh , Cutter, Daniel
IPC分类号： H03M7/40
摘要： An embodiment of an integrated circuit may comprise a hardware compressor to compress data, the hardware compressor including circuitry to store input data in a history buffer, compute one or more code tables based on the input data, and compute a compression stream header based on the computed one or more code tables. Other embodiments are disclosed and claimed.
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公开(公告)号：EP4016291A1
公开(公告)日：2022-06-22
申请号：EP22156135.0
申请日：2020-02-07
申请人： Intel Corporation
发明人： Shemy, Regev , Sperber, Zeev , Feghali, Wajdi , Gopal, Vinodh , Gradstein, Amit , Rubanovich, Simon , Gulley, Sean , Albrekht, Ilya , Doweck, Jacob , Yallouz, Jose , Anati, Ittai
IPC分类号： G06F9/30
摘要： Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor comprises a decode circuit to decode a first instruction, the first instruction comprising a plurality of fields to specify a first vector register and a second vector register, the first vector register to store a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register to store a fifth 64-bit data element; and an execution circuit coupled with the decode circuit. The execution circuit is to perform operations corresponding to the first instruction, including to: generate a result and store the result in the first vector register. The result is to include: a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the second 64-bit data element rotated right by one bit exclusive OR'd (XOR'd) with the second 64-bit data element rotated right by eight bits XOR'd with the second 64-bit data element shifted right by seven bits; a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the third 64-bit data element rotated right by one bit XOR'd with the third 64-bit data element rotated right by eight bits XOR'd with the third 64-bit data element shifted right by seven bits; a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the fourth 64-bit data element rotated right by one bit XOR'd with the fourth 64-bit data element rotated right by eight bits XOR'd with the fourth 64-bit data element shifted right by seven bits; and a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by one bit XOR'd with the fifth 64-bit data element rotated right by eight bits XOR'd with the fifth 64-bit data element shifted right by seven bits.
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公开(公告)号：EP2852088B1
公开(公告)日：2019-02-06
申请号：EP14169143.6
申请日：2008-03-25
申请人： Intel Corporation
发明人： Gueron, Shay , Feghali, Wajdi , Gopal, Vinodh , Raghunandan, Makaram , Dixon, Martin , Chennupaty, Srinivas , Kounavis, Michael
IPC分类号： H04L9/06 , H04L9/08 , G06F3/06 , G06F9/30 , G06F9/38 , G06F12/0862 , G06F12/0875 , G06F12/14 , G06F21/60 , G11C7/10
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公开(公告)号：EP4202692A1
公开(公告)日：2023-06-28
申请号：EP22203546.1
申请日：2022-10-25
申请人： INTEL Corporation
摘要： Apparatus and method for detecting a constant data block are described herein. An apparatus embodiment includes compression circuitry to perform compression operations on a memory block; constant detection circuitry to, concurrently with performance of the compression operations on the memory block, determine that the memory block is a constant data block comprised of only repeat instances of a constant value; and controller circuitry to associate a first indication with the memory block based on the determination, the first indication usable for controlling whether to abort the compression operations or whether to discard a compressed memory block generated from the compression operations.
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公开(公告)号：EP4149008A1
公开(公告)日：2023-03-15
申请号：EP22188197.2
申请日：2022-08-02
申请人： INTEL Corporation
摘要： Methods and apparatus relating to verifying a compressed stream fused with copy or transform operation(s) are described. In an embodiment, compression logic circuitry compresses input data and stores the compressed data in a temporary buffer. The compression logic circuitry determines a first checksum value corresponding to the compressed data stored in the temporary buffer. Decompression logic circuitry performs a decompress-verify operation and a copy operation. The decompress-verify operation decompresses the compressed data stored in the temporary buffer to determine a second checksum value corresponding to the decompressed data from the temporary buffer. The copy operation transfers the compressed data from the temporary buffer to a destination buffer in response to a match between the first checksum value and the second checksum value. Other embodiments are also disclosed and claimed.
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