公开(公告)号：EP4343635A1

公开(公告)日：2024-03-27

申请号：EP23186375.4

申请日：2023-07-19

申请人： INTEL Corporation

发明人： KADRI, Sudheendra ,  CREWS, Darren ,  MATHAIKUTTY, Deepak Abraham ,  DEIDDA, Andrea ,  RAHA, Arnab ,  BRADY, Kevin ,  BERNARD, David Thomas

IPC分类号： G06N3/063 ,  G06N3/0464 ,  G06F13/28 ,  G06N3/09

摘要： An DNN accelerator includes a DMA engine that can rearrange weight data layout. The DMA engine may read a weight tensor from a memory (e.g., DRAM). The weight tensor includes weights arranged in a 3D matrix. The DMA engine may partition the weight tensor into a plurality of virtual banks based on a structure of a PE array, e.g., based on the number of activated PE columns in the PE array. Then the DMA engine may partition a virtual bank into a plurality of virtual sub-banks. The DMA engine may also identify data blocks from different ones of the plurality of virtual sub-banks. A data block may include a plurality of input channels and may have a predetermined spatial size and storage size. The DMA engine form a linear data structure by interleaving the data blocks. The DMA engine can write the linear data structure into another memory (e.g., SRAM).