公开(公告)号：EP1902535A2

公开(公告)日：2008-03-26

申请号：EP06785547.8

申请日：2006-06-22

申请人： Intel Corporation ,  Li, Shenggao

发明人： CREWS, Darren ,  LIU, Chien-Chang ,  JOHNSTON, Robert

IPC分类号： H04B10/155 ,  H01S5/042

CPC分类号： H04B10/504

摘要： An electrical link driver for a point-to-point link is coupled to a laser. The electrical link driver provides a modulation current to the laser.

公开(公告)号：EP2691827A1

公开(公告)日：2014-02-05

申请号：EP11862131.7

申请日：2011-12-22

申请人： Intel Corporation

发明人： VILHAUER, Reed ,  CREWS, Darren ,  DURLEY, Paul ,  MULLEN, Kevin

IPC分类号： G05F1/66

CPC分类号： G06F1/3212 ,  G06F1/3206 ,  Y02D10/174

摘要： A power control manager includes a processor to compute available power from a power source and a comparator to compare the available power to an amount of power to concurrently operate a plurality of sub-systems of an electronic device at full or a predetermined power. The processor generates one or more control signals in response to a decision signal output from the comparator. The control signals may indicate that a maximum power setting is to be set for a first sub-system and a reduced non-zero power setting is to be set for a second sub-system of the plurality of sub-systems. The sub-systems may be different sub-systems of a smartphone or another electronic device.

公开(公告)号：EP1813004A2

公开(公告)日：2007-08-01

申请号：EP05851672.5

申请日：2005-11-09

申请人： Intel Corporation

发明人： CREWS, Darren

IPC分类号： H01S5/026 ,  H01S5/042 ,  H01S5/183 ,  G01R31/26

CPC分类号： H01S5/0261 ,  H01S5/0014 ,  H01S5/042 ,  H01S5/183 ,  H01S5/423

摘要： Reverse bias leakage testing may be used to determine the health of a vertical cavity surface emitting laser (VCSEL). When VCSELs are integrated on a die with other electronic devices such testing may damage the other electronic devices or be prohibited by circuits on the die designed to protect the electronics from being reverse biased. Accordingly, reverse bias testing may be facilitated by providing a second ground pad, separate from the die ground pad, specific to the VCSEL.

摘要翻译： 反向偏压泄漏测试可用于确定垂直腔面发射激光器（VCSEL）的健康状况。 当VCSEL与其他电子器件集成在芯片上时，这种测试可能会损坏其他电子器件或被芯片上的电路所禁止，以防止电子器件被反向偏置。 因此，通过提供专用于VCSEL的与管芯接地焊盘分离的第二接地焊盘可以促进反向偏置测试。

公开(公告)号：EP4343635A1

公开(公告)日：2024-03-27

申请号：EP23186375.4

申请日：2023-07-19

申请人： INTEL Corporation

发明人： KADRI, Sudheendra ,  CREWS, Darren ,  MATHAIKUTTY, Deepak Abraham ,  DEIDDA, Andrea ,  RAHA, Arnab ,  BRADY, Kevin ,  BERNARD, David Thomas

IPC分类号： G06N3/063 ,  G06N3/0464 ,  G06F13/28 ,  G06N3/09

摘要： An DNN accelerator includes a DMA engine that can rearrange weight data layout. The DMA engine may read a weight tensor from a memory (e.g., DRAM). The weight tensor includes weights arranged in a 3D matrix. The DMA engine may partition the weight tensor into a plurality of virtual banks based on a structure of a PE array, e.g., based on the number of activated PE columns in the PE array. Then the DMA engine may partition a virtual bank into a plurality of virtual sub-banks. The DMA engine may also identify data blocks from different ones of the plurality of virtual sub-banks. A data block may include a plurality of input channels and may have a predetermined spatial size and storage size. The DMA engine form a linear data structure by interleaving the data blocks. The DMA engine can write the linear data structure into another memory (e.g., SRAM).

公开(公告)号：EP1797620A1

公开(公告)日：2007-06-20

申请号：EP05809065.5

申请日：2005-09-30

申请人： Intel Corporation

发明人： CREWS, Darren ,  XU, Lee

IPC分类号： H01R12/20

CPC分类号： H05K1/182 ,  G02B6/42 ,  H01R12/714 ,  H01R12/722 ,  H01R13/6658 ,  H05K2201/10121 ,  H05K2201/10446

摘要： A circuit package includes a circuit substrate having a cutout portion defined therein, an interconnect electrically coupled to the circuit substrate and an active circuit component disposed off the circuit substrate within the cutout portion and electrically coupled to the interconnect. An optical circuit includes a lead frame and an optical component electrically coupled to the lead frame. The lead frame includes a first lead portion at a first level having an upper surface and a lower surface, and a second lead portion at a second level lower than the first level and electrically connected to the first lead portion. The lower surface of the first lead portion is arranged to electrically connect to a surface of a circuit substrate. The second lead portion includes an upper surface and a lower surface. The optical component is disposed on the upper surface of the second lead portion.