公开(公告)号：EP4328978A2

公开(公告)日：2024-02-28

申请号：EP23219358.1

申请日：2020-06-19

申请人： INTEL Corporation

发明人： METZ, Matthew ,  GSTREIN, Florian ,  MITAN, Martin ,  HOURANI, Rami ,  CLENDENNING, Scott ,  LIAO, Szuya ,  BAUMGARTEL, Lukas ,  CHIKKADI, Kiran ,  LANCASTER, Diane ,  TORRES, Jessica

IPC分类号： H01L29/78

摘要： Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：EP3796394A1

公开(公告)日：2021-03-24

申请号：EP20181036.3

申请日：2020-06-19

申请人： INTEL Corporation

发明人： METZ, Matthew ,  GSTREIN, Florian ,  MITAN, Martin ,  HOURANI, Rami ,  CLENDENNING, Scott ,  LIAO, Szuya ,  TORRES, Jessica ,  CHIKKADI, Kiran ,  BAUMGARTEL, Lukas ,  LANCASTER, Diane

IPC分类号： H01L29/66 ,  H01L29/78

摘要： Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：EP4328978A3

公开(公告)日：2024-04-24

申请号：EP23219358.1

申请日：2020-06-19

申请人： INTEL Corporation

发明人： METZ, Matthew ,  GSTREIN, Florian ,  MITAN, Martin ,  HOURANI, Rami ,  CLENDENNING, Scott ,  LIAO, Szuya ,  BAUMGARTEL, Lukas ,  CHIKKADI, Kiran ,  LANCASTER, Diane ,  TORRES, Jessica

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/775 ,  H01L21/823481 ,  H01L21/823475

摘要： Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：EP4203062A1

公开(公告)日：2023-06-28

申请号：EP22208658.9

申请日：2022-11-21

申请人： Intel Corporation

发明人： NANDI, Debaleena ,  BOMBERGER, Cory ,  LANCASTER, Diane ,  DEWEY, Gilbert ,  PATIL, Sandeep K. ,  KOBRINSKY, Mauro J. ,  MURTHY, Anand S. ,  GHANI, Tahir

IPC分类号： H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

摘要： Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires (406) above a sub-fin. A gate stack (428, 426) is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron, ii) a second pEPI region of silicon, germanium and boron on the first pEPI region at a contact location, iii) titanium silicide conductive contact material (434, 436) on the second pEPI region.