公开(公告)号：EP4443515A1

公开(公告)日：2024-10-09

申请号：EP23211498.3

申请日：2023-11-22

申请人： Intel Corporation

发明人： MANNEBACH, Ehren ,  MILLS, Shaun ,  D'SILVA, Joseph ,  KOBRINSKY, Mauro J. ,  ADB EI QADER, Makram

IPC分类号： H01L29/423 ,  H01L29/775 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8234

CPC分类号： H01L21/823475 ,  H01L29/41775 ,  H01L29/775 ,  H01L29/0673 ,  H01L21/823437 ,  H01L29/66439

摘要： Integrated circuit structures having backside contact widening are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate stack is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive gate contact is vertically beneath and in contact with a bottom of the gate stack. The conductive gate contact is in a cavity in an isolation layer, the cavity extending beyond the gate stack in a direction parallel with the epitaxial source or drain structure, and the cavity confined to the gate stack in a direction toward the epitaxial source or drain structure.

公开(公告)号：EP4443486A1

公开(公告)日：2024-10-09

申请号：EP23214546.6

申请日：2023-12-06

申请人： Samsung Electronics Co., Ltd.

发明人： KIM, Beom Jin ,  KIM, Guk Hee ,  KIM, Young Woo ,  KIM, Jun Soo ,  NA, Sang Cheol ,  LEE, Kyoung Woo ,  LEE, Anthony Dongick ,  LEE, Min Seung ,  CHAE, Myeong Gyoon ,  HA, Seung Seok

IPC分类号： H01L21/8234 ,  H01L21/48 ,  H01L27/088 ,  H01L29/417

CPC分类号： H01L21/823475 ,  H01L29/41766 ,  H01L29/775 ,  H01L27/088 ,  H01L29/4175 ,  H01L29/0673 ,  H01L29/66439

摘要： A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first horizontal direction on an upper surface of the substrate, a field insulating layer surrounding a sidewall of the active pattern on the upper surface of the substrate, a first gate electrode extending in a second horizontal direction intersecting the first horizontal direction on the active pattern, a source/drain region disposed on at least one side of the first gate electrode on the active pattern, an upper interlayer insulating layer covering the source/drain region on the field insulating layer, a through via penetrating through the substrate, the field insulating layer and the upper interlayer insulating layer in a vertical direction, the through via spaced apart from the source/drain region in the second horizontal direction, a source/drain contact disposed inside the upper interlayer insulating layer on at least one side of the first gate electrode, the source/drain contact connected to the source/drain region, and a connection portion disposed inside the upper interlayer insulating layer, the connection portion connected to each of the through via and the source/drain contact, wherein a width of the connection portion in the first horizontal direction is greater than a width of the source/drain contact in the first horizontal direction.

公开(公告)号：EP4441783A1

公开(公告)日：2024-10-09

申请号：EP21824524.9

申请日：2021-12-02

申请人： Imec VZW ,  Huawei Technologies Co., Ltd.

发明人： CHEHAB, Bilal ,  BHUWALKA, Krishna, Kumar ,  RYCKAERT, Julien

IPC分类号： H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/775

CPC分类号： H01L21/82385 ,  H01L27/092 ,  H01L21/823871 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/66439 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L27/0924 ,  H01L29/78696

公开(公告)号：EP4435847A1

公开(公告)日：2024-09-25

申请号：EP24151763.0

申请日：2024-01-15

申请人： Samsung Electronics Co., Ltd.

发明人： HWANG, Ingeon ,  KIM, Jinbum ,  KIM, Hyojin ,  LEE, Sangmoon ,  NAM, Yongjun ,  LEE, Taehyung

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/78696 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/42392 ,  H01L29/66545

摘要： An integrated circuit device (100) includes a fin-type active region (F1) on a substrate (102), a nanosheet (N1, N2; N3) on a fin top surface of the fin-type active region, the nanosheet being apart from the fin top surface of the fin-type active region in a vertical direction, a gate line (160) surrounding the nanosheet on the fin-type active region, and a source/drain region (130) on the fin-type active region, the source/drain region being in contact with the nanosheet, wherein the nanosheet includes a multilayered sheet comprising a first outer semiconductor sheet (S1), a core semiconductor sheet (S2), and a second outer semiconductor sheet (S3), which are sequentially stacked in the vertical direction.

公开(公告)号：EP4435844A1

公开(公告)日：2024-09-25

申请号：EP24164411.1

申请日：2024-03-19

申请人： Samsung Electronics Co., Ltd.

发明人： YOO, Donggon

IPC分类号： H01L21/822 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L23/48 ,  H01L29/417 ,  H01L29/775 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/8221 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0688 ,  H01L21/76898 ,  H01L29/41725 ,  H01L29/66439 ,  H01L29/775 ,  H01L23/481 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L23/485 ,  H01L21/76805 ,  H01L21/76897

摘要： A semiconductor device includes: insulating patterns; a device isolation layer on side surfaces of the insulating patterns; gate structures; source/drain regions (150) on the insulating patterns; a via structure (190) between the gate structures and between the source/drain regions; and contact structures (180) connected to the source/drain regions and the via structure, wherein the source/drain regions may include first source/drain regions (150A) and second source/drain regions (150B), wherein the via structure may extend from the same level as lower surfaces of the first source/drain regions to the same level as upper surfaces of the second source/drain regions, and the via structure may include a portion in which a width of the via structure increases and then decreases or decreases and then increases, wherein the contact structures may include a first contact structure contacting the first source/drain regions and a second contact structure contacting the second source/drain regions.

公开(公告)号：EP4428910A2

公开(公告)日：2024-09-11

申请号：EP23220088.1

申请日：2023-12-22

申请人： INTEL Corporation ,  Golonzka, Oleg

发明人： GOLONZKA, Oleg ,  XU, Guowei ,  HUANG, Chiao-Ti ,  CHAO, Robin ,  CHU, Tao ,  ZHANG, Feng ,  ZHANG, Yang ,  GUHA, Biswajeet

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L21/823481 ,  H01L27/088 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/0673

摘要： An IC device includes a backside fin trim isolation (FTI, 150) separating a first transistor (170A) from a second transistor (170B). The FTI may be between a source region of the first transistor and a drain region of the second transistor. The source region of the first transistor and the drain region of the second transistor may be different portions of a semiconductor structure, e.g., a fin or nanoribbon. The IC device may also include a frontside metal layer (125). The semiconductor structure has a first surface and a second surface opposing the first surface. The first surface of the semiconductor structure is closer to the metal layer and may be larger than the second surface of the semiconductor structure. The FTI may has a first surface and a second surface opposing the first surface. The first surface of the FTI is closer to the metal layer but may be smaller than the second surface of the FTI.

公开(公告)号：EP4423810A1

公开(公告)日：2024-09-04

申请号：EP22798380.6

申请日：2022-10-14

申请人： International Business Machines Corporation

发明人： XIE, Ruilong ,  CHENG, Kangguo ,  FROUGIER, Julien ,  PARK, Chanro

IPC分类号： H01L23/528

CPC分类号： H01L23/5286 ,  H01L29/78696 ,  H01L23/535 ,  H01L21/76897 ,  H01L21/76895 ,  H01L21/76883 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/0673 ,  B82Y10/00 ,  H01L29/66545 ,  H01L29/165 ,  H01L29/41725

公开(公告)号：EP4325580A3

公开(公告)日：2024-09-04

申请号：EP23220604.5

申请日：2022-10-13

申请人： INTEL Corporation

发明人： GULER, Leonard P. ,  GHANI, Tahir ,  WALLACE, Charles H. ,  HARAN, Mohit K. ,  HASAN, Mohammad ,  NAVABI-SHIRAZI, Aryan ,  GARDINER, Allen B.

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/786 ,  B82Y10/00

CPC分类号： B82Y10/00 ,  H01L29/66439 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/42392 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0847 ,  H01L21/823412 ,  H01L29/66545 ,  H01L29/78696

摘要： Integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, and methods of fabricating integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A confined epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure, the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure.

公开(公告)号：EP4404252A2

公开(公告)日：2024-07-24

申请号：EP23217582.8

申请日：2023-12-18

申请人： Samsung Electronics Co., Ltd.

发明人： BAEK, Jaejik ,  YUN, Seungchan ,  SEO, Kang-ill

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/088 ,  H01L27/0688 ,  H01L21/8221 ,  H01L21/823462 ,  H01L21/82345 ,  H01L21/823481 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/78696

摘要： Provided is a three-dimensionally-stacked field-effect transistor, 3DSFET, device including a plurality of 3DSFET structures on a single substrate, wherein each of the 3DSFET structures includes: a 1st channel structure surrounded by a 1st gate structure; and a 2nd channel structure surrounded by a 2nd gate structure, the 2nd channel structure provided on the 1st channel structure, and wherein, in at least one of the 3DSFETs, the 1st gate structure is isolated from the 2nd gate structure through a barrier layer including a dielectric material comprising tantalum.

公开(公告)号：EP4396866A1

公开(公告)日：2024-07-10

申请号：EP22865544.5

申请日：2022-09-01

申请人： Applied Materials, Inc.

发明人： PARIKH, Suketu Arun ,  PAL, Ashish ,  BAZIZI, El Mehdi ,  YEOH, Andrew ,  INGLE, Nitin K. ,  SUNDARRAJAN, Arvind ,  SEE, Guan Huei ,  BERKENS, Martinus Maria ,  DESHPANDE, Sameer A. ,  PRANATHARTHIHARAN, Balasubramanian ,  YANG, Yen-Chu

IPC分类号： H01L21/8234 ,  H01L21/18 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L21/823475 ,  H01L21/76251 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66439 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/4175 ,  H01L23/5286 ,  H01L21/76895 ,  H01L21/76898 ,  H01L29/78687 ,  H01L21/76897