公开(公告)号：EP4328978A2

公开(公告)日：2024-02-28

申请号：EP23219358.1

申请日：2020-06-19

申请人： INTEL Corporation

发明人： METZ, Matthew ,  GSTREIN, Florian ,  MITAN, Martin ,  HOURANI, Rami ,  CLENDENNING, Scott ,  LIAO, Szuya ,  BAUMGARTEL, Lukas ,  CHIKKADI, Kiran ,  LANCASTER, Diane ,  TORRES, Jessica

IPC分类号： H01L29/78

摘要： Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：EP3796394A1

公开(公告)日：2021-03-24

申请号：EP20181036.3

申请日：2020-06-19

申请人： INTEL Corporation

发明人： METZ, Matthew ,  GSTREIN, Florian ,  MITAN, Martin ,  HOURANI, Rami ,  CLENDENNING, Scott ,  LIAO, Szuya ,  TORRES, Jessica ,  CHIKKADI, Kiran ,  BAUMGARTEL, Lukas ,  LANCASTER, Diane

IPC分类号： H01L29/66 ,  H01L29/78

摘要： Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：EP4328978A3

公开(公告)日：2024-04-24

申请号：EP23219358.1

申请日：2020-06-19

申请人： INTEL Corporation

发明人： METZ, Matthew ,  GSTREIN, Florian ,  MITAN, Martin ,  HOURANI, Rami ,  CLENDENNING, Scott ,  LIAO, Szuya ,  BAUMGARTEL, Lukas ,  CHIKKADI, Kiran ,  LANCASTER, Diane ,  TORRES, Jessica

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/775 ,  H01L21/823481 ,  H01L21/823475

摘要： Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：EP3929150A1

公开(公告)日：2021-12-29

申请号：EP20208051.1

申请日：2020-11-17

申请人： INTEL Corporation

发明人： CHOUKSEY, Siddharth ,  AGRAWAL, Ashish ,  SUNG, Seung ,  KAVALIEROS, Jack ,  METZ, Mathew ,  RACHMADY, Willy ,  TORRES, Jessica ,  MITAN, Martin

IPC分类号： B82Y10/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775

摘要： Embodiments disclosed herein include nanowire or nanoribbon semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of semiconductor nanowire or nanoribbon channels (410) with a first end and second end. Individual ones of the semiconductor channels comprise a nitrided surface (415), formed by a plasma treatment of the semiconductor channels. The semiconductor device further comprises a source region (405) at the first end of the stack, a drain region (405) at the second end of the stack, a gate dielectric (417) surrounding the nitrided semiconductor channels, and a gate electrode (419) surrounding the gate dielectric.