公开(公告)号：EP3702940A1

公开(公告)日：2020-09-02

申请号：EP20152535.9

申请日：2020-01-17

申请人： INTEL Corporation

发明人： NARAYANAMOORTHY, Srinivasan ,  BOBBA, Jayaram ,  MORE, Ankit

IPC分类号： G06F17/16

摘要： The present disclosure is directed to systems and methods for decomposing systolic array circuitry to provide a plurality of N x N systolic sub-array circuits, apportioning a first tensor or array into a plurality of N x M first input arrays, and apportioning a second tensor or array into a plurality of M x N second input arrays. Systolic array control circuitry transfers corresponding ones of the first input arrays and second input arrays to a respective one of the plurality of N x N systolic sub-array circuits. As the elements included in the first input array and the elements included in the second input array are transferred to the systolic sub-array, the systolic sub-array performs one or more mathematical operations using the first and the second input arrays. The systems and methods beneficially improve the usage of the systolic array circuitry thereby advantageously reducing the number of clock cycles needed to perform a given number of calculations.

公开(公告)号：EP3588297A1

公开(公告)日：2020-01-01

申请号：EP19175809.3

申请日：2019-05-21

申请人： INTEL Corporation

发明人： PAWLOWSKI, Robert ,  MORE, Ankit ,  SMITH, Shaden ,  PITCHAIMOORTHY, Sowmya ,  JAIN, Samkit ,  CAVÉ, Vincent ,  AANANTHAKRISHNAN, Sriram ,  HOWARD, Jason M. ,  FRYMAN, Joshua B.

IPC分类号： G06F9/52

摘要： In one embodiment, a first processor core includes: a plurality of execution pipelines each to execute instructions of one or more threads; a plurality of pipeline barrier circuits coupled to the plurality of execution pipelines, each of the plurality of pipeline barrier circuits associated with one of the plurality of execution pipelines to maintain status information for a plurality of barrier groups, each of the plurality of barrier groups formed of at least two threads; and a core barrier circuit to control operation of the plurality of pipeline barrier circuits and to inform the plurality of pipeline barrier circuits when a first barrier has been reached by a first barrier group of the plurality of barrier groups. Other embodiments are described and claimed.

公开(公告)号：EP3588288A1

公开(公告)日：2020-01-01

申请号：EP19177145.0

申请日：2019-05-28

申请人： INTEL Corporation

发明人： GRIFFIN, Paul ,  FRYMAN, Joshua ,  HOWARD, Jason ,  PARK, Sang Phill ,  PAWLOWSKI, Robert ,  ABBOTT, Michael ,  CLINE, Scott ,  JAIN, Samkit ,  MORE, Ankit ,  CAVE, Vincent ,  PETRINI, Fabrizio ,  GANEV, Ivan

IPC分类号： G06F9/48

摘要： Embodiments of apparatuses, methods, and systems for a multithreaded processor core with hardware-assisted task scheduling are described. In an embodiment, a processor includes a first hardware thread, a second hardware thread, and a task manager. The task manager is to issue a task to the first hardware thread. The task manager includes a hardware task queue in which to store a plurality of task descriptors. Each of the task descriptors is to represent one of a single task, a collection of iterative tasks, and a linked list of tasks.