公开(公告)号：EP3037976B1

公开(公告)日：2018-01-03

申请号：EP15195491.4

申请日：2015-11-19

申请人： Intel Corporation

发明人： KWON, Kon-Woo ,  SOMASEKHAR, Dinesh ,  PARK, Sang Phill

IPC分类号： G06F13/42

CPC分类号： H03M13/19 ,  G06F13/4221 ,  G06F13/4234 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

摘要： Methods and apparatus relating to enhanced Data Bus Invert (EDBI) encoding for OR chained buses are described. In an embodiment, incoming data on a bus is encoded based at least in part on a determination of whether a next data value on the bus is going to transitioning from a valid value to a parked state. Other embodiments are also disclosed.

公开(公告)号：EP3588288A1

公开(公告)日：2020-01-01

申请号：EP19177145.0

申请日：2019-05-28

申请人： INTEL Corporation

发明人： GRIFFIN, Paul ,  FRYMAN, Joshua ,  HOWARD, Jason ,  PARK, Sang Phill ,  PAWLOWSKI, Robert ,  ABBOTT, Michael ,  CLINE, Scott ,  JAIN, Samkit ,  MORE, Ankit ,  CAVE, Vincent ,  PETRINI, Fabrizio ,  GANEV, Ivan

IPC分类号： G06F9/48

摘要： Embodiments of apparatuses, methods, and systems for a multithreaded processor core with hardware-assisted task scheduling are described. In an embodiment, a processor includes a first hardware thread, a second hardware thread, and a task manager. The task manager is to issue a task to the first hardware thread. The task manager includes a hardware task queue in which to store a plurality of task descriptors. Each of the task descriptors is to represent one of a single task, a collection of iterative tasks, and a linked list of tasks.

公开(公告)号：EP3037976A1

公开(公告)日：2016-06-29

申请号：EP15195491.4

申请日：2015-11-19

申请人： Intel Corporation

发明人： KWON, Kon-Woo ,  SOMASEKHAR, Dinesh ,  PARK, Sang Phill

IPC分类号： G06F13/42

CPC分类号： H03M13/19 ,  G06F13/4221 ,  G06F13/4234 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

摘要： Methods and apparatus relating to enhanced Data Bus Invert (EDBI) encoding for OR chained buses are described. In an embodiment, incoming data on a bus is encoded based at least in part on a determination of whether a next data value on the bus is going to transitioning from a valid value to a parked state. Other embodiments are also disclosed.

摘要翻译： 描述与OR链接总线的增强数据总线反相（EDBI）编码有关的方法和设备。 在一个实施例中，总线上的输入数据至少部分地基于总线上的下一个数据值是否将从有效值转换到停止状态的确定进行编码。 还公开了其它实施例。

公开(公告)号：EP3238001A1

公开(公告)日：2017-11-01

申请号：EP15873969.8

申请日：2015-11-23

申请人： Intel Corporation

发明人： KIM, Young Moon ,  PARK, Sang Phill

IPC分类号： G06F1/32 ,  G06F9/30

CPC分类号： G06T1/20 ,  G06F1/32 ,  G06F9/30098 ,  G06F9/30141 ,  G06F9/3016 ,  G09G5/00 ,  G09G5/363 ,  G09G2330/021 ,  H03M7/00 ,  H03M7/24 ,  H03M13/1108

摘要： An apparatus and method are described for reducing power when reading and writing graphics data. For example, one embodiment of an apparatus comprises: a graphics processor unit (GPU) to process graphics data including floating point data; a set of registers, at least one of the registers of the set partitioned to store the floating point data; and encode/decode logic to reduce a number of binary 1 values being read from the at least one register by causing a specified set of bit positions within the floating point data to be read out as 0s rather than 1s.

摘要翻译： 描述了用于在读取和写入图形数据时降低功率的设备和方法。 例如，设备的一个实施例包括：图形处理器单元（GPU），用于处理包括浮点数据的图形数据; 一组寄存器，该组中的至少一个寄存器被分区以存储浮点数据; 以及编码/解码逻辑，以通过使得浮点数据内的指定的一组比特位置被读出为0而不是1来减少从该至少一个寄存器读取的二进制1值的数目。