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公开(公告)号:EP4258334A1
公开(公告)日:2023-10-11
申请号:EP23157084.7
申请日:2023-02-16
申请人: INTEL Corporation
发明人: ONG, Clifford , GULER, Leonard P. , SHRIDHARAN, Smita , GUO, Zheng , WALLACE, Charles H. , KARL, Eric , KOBRINSKY, Mauro J. , OGADHOH, Shem , GHANI, Tahir
IPC分类号: H01L21/8234 , H01L27/088 , H10B10/00 , H01L29/423 , H01L29/786 , H01L29/66 , H01L23/48 , H01L21/768
摘要: Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BMO) and a backside of an epitaxial structure, as well as electrical connection structures that electrically couple the BMO to a front side of an epitaxial structure. Other embodiments may be described and/or claimed.
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公开(公告)号:EP4109536A1
公开(公告)日:2022-12-28
申请号:EP22179999.2
申请日:2022-06-20
申请人: INTEL Corporation
发明人: ALZATE VINASCO, Juan , LAJOIE, Travis W. , TAN, Elliot , PIERCE, Kimberly , OGADHOH, Shem , SHARMA, Abhishek Anil , SELL, Bernhard , WANG, Pei-Hua , KU, Chieh-Jen
IPC分类号: H01L27/108
摘要: A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.
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