MULTILEVEL WORDLINE ASSEMBLY FOR EMBEDDED DRAM

    公开(公告)号:EP4109536A1

    公开(公告)日:2022-12-28

    申请号:EP22179999.2

    申请日:2022-06-20

    申请人: INTEL Corporation

    IPC分类号: H01L27/108

    摘要: A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.