公开(公告)号：EP4345875A1

公开(公告)日：2024-04-03

申请号：EP23185054.6

申请日：2023-07-12

申请人： INTEL Corporation

发明人： GULER, Leonard P. ,  ONG, Clifford ,  YEMENICIOGLU, Sukru ,  GHANI, Tahir

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/775

摘要： Integrated circuit structures having fin-shaped isolation regions recessed for gate contact are described. An integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure (110A, 112A) is over the vertical stack of horizontal nanowires (108) and on the first sub-fin. A dielectric structure (130A) is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A dielectric gate cut plug (122B) is between the gate structure and the dielectric structure. A recess is in the dielectric structure and in the dielectric gate cut plug. A conductive structure (154) is in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure.

公开(公告)号：EP4195286A1

公开(公告)日：2023-06-14

申请号：EP22204907.4

申请日：2022-11-01

申请人： INTEL Corporation

发明人： GULER, Leonard P. ,  ONG, Clifford ,  HASAN, Mohammad ,  GHANI, Tahir ,  WALLACE, Charles H.

IPC分类号： H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

摘要： Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a directed bottom-up approach, are described. An integrated circuit structure includes a vertical arrangement of nanowires (210B) above a substrate (202). A gate stack (204) is over and around the vertical arrangement of nanowires. A first epitaxial source or drain structure (220B) is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires, the second end opposite the first end, wherein at least one of the first or second epitaxial source or drain structures is coupled to fewer than all nanowires of the vertical arrangement of nanowires.

公开(公告)号：EP4148776A1

公开(公告)日：2023-03-15

申请号：EP22189218.5

申请日：2022-08-08

申请人： INTEL Corporation

发明人： HASAN, Mohammad ,  GHANI, Tahir ,  PATEL, Pratik ,  GULER, Leonard ,  ONG, Clifford ,  HARAN, Mohit

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06

摘要： Techniques are provided herein to form semiconductor devices having a different number of semiconductor nanoribbons compared to other semiconductor devices on the same substrate. In one example, two different semiconductor devices of a given memory cell, such as a random access memory (RAM) cell, include a p-channel device and an n-channel device. More specifically, the p-channel device (102) may be a GAA transistor with a first number of semiconductor nanoribbons (112a) while the n-channel device (104) may be a GAA transistor with a second number of semiconductor nanoribbons (112b) that is greater than the first number of semiconductor nanoribbons. In some cases, the n-channel device(s) have one additional semiconductor nanoribbon compared to the p-channel device(s). Depending on when the nanoribbons are removed during the fabrication process, different structural outcomes will occur that can be detected in the final device.

公开(公告)号：EP4258334A1

公开(公告)日：2023-10-11

申请号：EP23157084.7

申请日：2023-02-16

申请人： INTEL Corporation

发明人： ONG, Clifford ,  GULER, Leonard P. ,  SHRIDHARAN, Smita ,  GUO, Zheng ,  WALLACE, Charles H. ,  KARL, Eric ,  KOBRINSKY, Mauro J. ,  OGADHOH, Shem ,  GHANI, Tahir

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H10B10/00 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L23/48 ,  H01L21/768

摘要： Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BMO) and a backside of an epitaxial structure, as well as electrical connection structures that electrically couple the BMO to a front side of an epitaxial structure. Other embodiments may be described and/or claimed.

公开(公告)号：EP4148804A1

公开(公告)日：2023-03-15

申请号：EP22190217.4

申请日：2022-08-12

申请人： Intel Corporation

发明人： HASAN, Mohammad ,  GHANI, Tahir ,  PATEL, Pratik ,  GULER, Leonard P. ,  HARAN, Mohit ,  ONG, Clifford

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/78

摘要： Techniques are provided herein to form semiconductor devices having thinned semiconductor regions (e.g., thinner nanoribbons) compared to other semiconductor devices on the same substrate and at a comparable height (e.g., within same layer or adjacent layers). In an example, neighboring semiconductor devices of a given memory cell include a p-channel device and an n-channel device. The p-channel device may be a GAA transistor with a semiconductor nanoribbon having a first width while the n-channel device may be a GAA transistor with a semiconductor nanoribbon having a second width that is larger than the first width (e.g., first width is half the second width). The p-channel device may have a thinner width than the corresponding n-channel device in order to structurally lower the operating current through the p-channel devices by decreasing the width of the active semiconductor channel.

公开(公告)号：EP4203643A1

公开(公告)日：2023-06-28

申请号：EP22214738.1

申请日：2022-12-19

申请人： INTEL Corporation

发明人： ONG, Clifford ,  GULER, Leonard P. ,  SHRIDHARAN, Smita ,  GUO, Zheng ,  KARL, Eric ,  GHANI, Tahir

IPC分类号： H10B10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

摘要： Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.

公开(公告)号：EP4203642A1

公开(公告)日：2023-06-28

申请号：EP22208799.1

申请日：2022-11-22

申请人： INTEL Corporation

发明人： ONG, Clifford ,  GULER, Leonard ,  HASAN, Mohammad ,  GHANI, Tahir

IPC分类号： H10B10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

摘要： Integrated circuit (IC) static random-access memory (SRAM) bit-cell structures comprising pass-gate transistors (130) having a different number of active channel regions than the number of active channel regions in pull-down transistors (125). A pass-gate transistor with fewer active channel regions than a pull-down transistor may reduce read instability of an SRAM bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, one or more pass-gate transistor channel regions (605) are impurity doped or removed from either a top side or bottom side of the pass-gate transistors to depopulate the number of active channel regions relative to a pull-down transistor.

公开(公告)号：EP4203641A1

公开(公告)日：2023-06-28

申请号：EP22205746.5

申请日：2022-11-07

申请人： INTEL Corporation

发明人： ONG, Clifford ,  LAVRIC, Dan ,  GULER, Leonard ,  CHIU Yen Ting ,  SHRIDHARAN, Smita ,  GUO, Zheng ,  KARL, Eric A. ,  GHANI, Tahir

IPC分类号： H10B10/00 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

摘要： Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors (292) and pull-down transistors (291) having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.