公开(公告)号：EP3729495A1

公开(公告)日：2020-10-28

申请号：EP17935707.4

申请日：2017-12-22

申请人： INTEL Corporation

发明人： LAJOIE, Travis ,  GHANI, Tahir ,  KAVALIEROS, Jack T. ,  OGADHOH, Shem O. ,  WANG, Yih ,  SELL, Bernhard ,  GARDINER, Allen ,  LIN, Blake ,  ALZATE VINASCO, Juan G. ,  WANG, Pei-Hua ,  KU, Chieh-Jen ,  SHARMA, Abhishek A.

IPC分类号： H01L21/768

公开(公告)号：EP4016624A1

公开(公告)日：2022-06-22

申请号：EP21194975.5

申请日：2021-09-06

申请人： INTEL Corporation

发明人： SATO, Noriyuki ,  ATANASOV, Sarah ,  SHARMA, Abhishek ,  SELL, Bernhard ,  KU, Chieh-Jen ,  SEN GUPTA, Arnab ,  METZ, Matthew ,  TAN, Elliot ,  YOO, Hui ,  LAJOIE, Travis ,  LE, Van ,  WANG, Pei-Hua

IPC分类号： H01L27/108

摘要： An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

公开(公告)号：EP4109536A1

公开(公告)日：2022-12-28

申请号：EP22179999.2

申请日：2022-06-20

申请人： INTEL Corporation

发明人： ALZATE VINASCO, Juan ,  LAJOIE, Travis W. ,  TAN, Elliot ,  PIERCE, Kimberly ,  OGADHOH, Shem ,  SHARMA, Abhishek Anil ,  SELL, Bernhard ,  WANG, Pei-Hua ,  KU, Chieh-Jen

IPC分类号： H01L27/108

摘要： A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.

公开(公告)号：EP4016642A1

公开(公告)日：2022-06-22

申请号：EP21198468.7

申请日：2021-09-23

申请人： Intel Corporation

发明人： SATO, Noriyuki ,  ATANASOV, Sarah ,  SHARMA, Abhishek Anil ,  SELL, Bernhard ,  KU, Chieh-Jen ,  TAN, Elliot ,  YOO, Hui Jae ,  LAJOIE, Travis ,  LE, Van ,  WANG, Pei-Hua ,  PECK, Jason ,  BROWN-HEFT, Tobias

IPC分类号： H01L29/66 ,  H01L29/78

摘要： Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed

公开(公告)号：EP3975276A1

公开(公告)日：2022-03-30

申请号：EP21193106.8

申请日：2021-08-25

申请人： INTEL Corporation

发明人： SELL, Bernhard ,  WANG, Pei-Hua ,  KU, Chieh-Jen

IPC分类号： H01L49/02 ,  H01L27/06 ,  H01L27/08

摘要： Tunable resistance thin film resistors for integrated circuits, related systems, and methods of fabrication are disclosed. Such tunable resistance thin film resistors include electrodes coupled to a resistive thin film that includes a base metal oxide and a second metal element. The resistors are tunable based on the concentration of the second metal element in the composition of the resistive thin film.