公开(公告)号：EP4345880A1

公开(公告)日：2024-04-03

申请号：EP23193414.2

申请日：2023-08-25

申请人： INTEL Corporation

发明人： BAYATI, Reza ,  PRINCE, Matthew ,  DAVIS, Alison ,  GHOSTINE, Ramy ,  SINHA, Piyush ,  GOLONZKA, Oleg ,  GHOSH, Swapnadip ,  SHARMA, Manish

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

摘要： Techniques are provided herein to form semiconductor devices (101, 103) that include one or more gate cuts (120) having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater, such as 10: 1). In an example, a semiconductor device includes a conductive material (118a, 118b) that is part of a transistor gate structure around or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material that extends between a source region and a drain region, or one or more nanowires or nanoribbons of semiconductor material (104) that extend between a source region and a drain region. The gate structure may be interrupted between two transistors (101, 103) with a gate cut (120) that extends through an entire thickness of the gate structure. A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio so as to enable densely integrated devices.

公开(公告)号：EP4439675A2

公开(公告)日：2024-10-02

申请号：EP23214822.1

申请日：2023-12-07

申请人： INTEL Corporation

发明人： KOH, Shao-Ming ,  MORROW, Patrick ,  MEHTA, Nikhil ,  GULER, Leonard ,  NASKAR, Sudipto ,  DAVIS, Alison ,  LAVRIC, Dan ,  PRINCE, Matthew ,  LUCE, Jeanne ,  WALLACE, Charles ,  VOGELSBERG, Cortnie ,  PAI, Rajaram ,  KILROY, Caitlin ,  AMONOO, Jojo ,  PURSEL, Sean ,  GOTLIB, Yulia

IPC分类号： H01L29/423 ,  H01L29/775 ,  H01L29/06

CPC分类号： H01L29/775 ,  H01L29/0673 ,  H01L29/42376

摘要： Transistor structures comprising a gate electrode, or "gate," that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.

公开(公告)号：EP4439675A3

公开(公告)日：2024-11-13

申请号：EP23214822.1

申请日：2023-12-07

申请人： INTEL Corporation

发明人： KOH, Shao-Ming ,  MORROW, Patrick ,  MEHTA, Nikhil ,  GULER, Leonard ,  NASKAR, Sudipto ,  DAVIS, Alison ,  LAVRIC, Dan ,  PRINCE, Matthew ,  LUCE, Jeanne ,  WALLACE, Charles ,  VOGELSBERG, Cortnie ,  PAI, Rajaram ,  KILROY, Caitlin ,  AMONOO, Jojo ,  PURSEL, Sean ,  GOTLIB, Yulia

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06

摘要： Transistor structures comprising a gate electrode, or "gate," that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.