公开(公告)号：EP4359883A1

公开(公告)日：2024-05-01

申请号：EP22828932.8

申请日：2022-03-23

申请人： INTEL Corporation

发明人： SHAH, Pritesh P. ,  CHEMUDUPATI, Suresh ,  GENDLER, Alexander ,  HUNT, David ,  MACNAMARA, Christopher M. ,  NATHAN, Ofer ,  PURANDARE, Adwait ,  VARMA, Ankush

IPC分类号： G06F1/3209 ,  G06F1/324 ,  G06F1/3234

CPC分类号： Y02D10/00 ,  G06F9/5094 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3228

公开(公告)号：EP4109217A3

公开(公告)日：2023-01-25

申请号：EP22161848.1

申请日：2022-03-14

申请人： Intel Corporation

发明人： PURANDARE, Adwait ,  STEINER, Ian ,  CHEN, Stanley ,  GUPTA, Nikhil ,  SRINIVASAN, Vasudevan ,  VARMA, Ankush

IPC分类号： G06F1/3203

摘要： In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.

公开(公告)号：EP4217823A1

公开(公告)日：2023-08-02

申请号：EP21873565.2

申请日：2021-09-24

申请人： INTEL Corporation

发明人： GARG, Vivek ,  VARMA, Ankush ,  SISTLA, Krishnakanth ,  GUPTA, Nikhil ,  BALIGAR, Nikethan Shivanand ,  WANG, Stephen ,  PALIT, Nilanjan ,  KAM, Timothy ,  PURANDARE, Adwait ,  GUPTA, Ujjwal ,  CHEN, Stanley ,  SHAPIRA, Dorit ,  VENUGOPAL, Shruthi ,  CHEMUDUPATI, Suresh ,  PARIKH, Rupal ,  DEHAEMER, Eric ,  SAMPATH, Pavithra ,  KANDULA, Phani Kumar ,  BANSAL, Yogesh ,  MULLA, Dean ,  TULANOWSKI, Michael ,  HAAKE, Stephen ,  HERDRICH, Andrew ,  DAS, Ripan

IPC分类号： G06F1/3203 ,  G06F1/30 ,  G06F1/26 ,  G06F9/50

公开(公告)号：EP4109217A2

公开(公告)日：2022-12-28

申请号：EP22161848.1

申请日：2022-03-14

申请人： Intel Corporation

发明人： PURANDARE, Adwait ,  STEINER, Ian ,  CHEN, Stanley ,  GUPTA, Nikhil ,  SRINIVASAN, Vasudevan ,  VARMA, Ankush

IPC分类号： G06F1/3203

摘要： In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.