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公开(公告)号：EP3382500A1
公开(公告)日：2018-10-03
申请号：EP18154432.1
申请日：2018-01-31
申请人： Intel Corporation
CPC分类号： H04L47/2425 , G06F1/206 , G06F1/28 , G06F1/30 , G06F1/3206 , G06F1/324 , G06F1/3296 , G06F9/5044 , G06F9/5094 , G06F11/3058 , H04L41/5022 , H04L47/805 , H04L67/1008 , H04L67/12 , Y02D10/126 , Y02D10/172
摘要： A rack system including a plurality of nodes can implement thermal/power throttling, sub-node composition, and processing balancing based on voltage/frequency. In the thermal/power throttling, at least one resource is throttled, based at least in part on a heat event or a power event. In the sub-node composition, a plurality of computing cores is divided into a target number of domains. In the processing balancing based on voltage/frequency, a first core performs a first processing job at a first voltage or frequency, and a second core performs a second processing job at a second voltage or frequency different from the first voltage or frequency.
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公开(公告)号：EP4338073A1
公开(公告)日：2024-03-20
申请号：EP22726926.3
申请日：2022-05-10
申请人： Intel Corporation
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公开(公告)号：EP4109217A3
公开(公告)日：2023-01-25
申请号：EP22161848.1
申请日：2022-03-14
申请人： Intel Corporation
发明人： PURANDARE, Adwait , STEINER, Ian , CHEN, Stanley , GUPTA, Nikhil , SRINIVASAN, Vasudevan , VARMA, Ankush
IPC分类号： G06F1/3203
摘要： In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.
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4.发明公开
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公开(公告)号：EP4109217A2
公开(公告)日：2022-12-28
申请号：EP22161848.1
申请日：2022-03-14
申请人： Intel Corporation
发明人： PURANDARE, Adwait , STEINER, Ian , CHEN, Stanley , GUPTA, Nikhil , SRINIVASAN, Vasudevan , VARMA, Ankush
IPC分类号： G06F1/3203
摘要： In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.
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公开(公告)号：EP4035116A1
公开(公告)日：2022-08-03
申请号：EP20868873.9
申请日：2020-09-25
申请人： Intel Corporation
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公开(公告)号：EP3259652A1
公开(公告)日：2017-12-27
申请号：EP16752781.1
申请日：2016-01-27
申请人： Intel Corporation
发明人： VARMA, Ankush , SISTLA, Krishnakanth V. , SRINIVASAN, Vasudevan , GORBATOV, Eugene , HENROID, Andrew D. , COOPER, Barnes , BROWNING, David W. , THERIEN, Guy M. , SONGER, Neil W. , HERMERDING II, James G.
CPC分类号： G06F1/3206 , G06F1/3203 , G06F1/3287 , G06F9/50 , Y02B70/126 , Y02D10/171
摘要： In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.
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