公开(公告)号：EP3969984A1

公开(公告)日：2022-03-23

申请号：EP20806293.5

申请日：2020-03-19

申请人： INTEL Corporation

发明人： ANANTHAKRISHNAN, Avinash N. ,  AMBARDEKAR, Ameya ,  VARMA, Ankush ,  ANGEL, Nimrod ,  ROSENZWEIG, Nir ,  GIHON, Arik ,  GENDLER, Alexander ,  RAYESS, Rachid E. ,  SALUS, Tamir

IPC分类号： G06F1/3234 ,  G06F1/3296

公开(公告)号：EP4359883A1

公开(公告)日：2024-05-01

申请号：EP22828932.8

申请日：2022-03-23

申请人： INTEL Corporation

发明人： SHAH, Pritesh P. ,  CHEMUDUPATI, Suresh ,  GENDLER, Alexander ,  HUNT, David ,  MACNAMARA, Christopher M. ,  NATHAN, Ofer ,  PURANDARE, Adwait ,  VARMA, Ankush

IPC分类号： G06F1/3209 ,  G06F1/324 ,  G06F1/3234

CPC分类号： Y02D10/00 ,  G06F9/5094 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3228

公开(公告)号：EP3314428A1

公开(公告)日：2018-05-02

申请号：EP16814946.6

申请日：2016-05-25

申请人： Intel Corporation

发明人： VARMA, Ankush ,  FLEMING, Kristoffer D. ,  GORBATOV, Eugene ,  GOUGH, Robert E. ,  SISTLA, Krishnakanth V.

IPC分类号： G06F9/48 ,  G06F9/38

CPC分类号： G06F9/4893 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/455

摘要： An apparatus and method for performing high performance instruction emulation. One embodiment of the invention includes a processor to process an instruction set including high-power and standard instructions comprising: an analysis module to determine whether a number of high-power instructions within a specified window are above or below a specified threshold; an execution mode selection module to select a native execution of the high-power instructions if the number of high-power instructions are above the specified threshold or to select an emulated execution of the high-power instructions if the number of high-power instructions are below the specified threshold.

公开(公告)号：EP3949098A1

公开(公告)日：2022-02-09

申请号：EP20783924.2

申请日：2020-02-25

申请人： INTEL Corporation

发明人： SALUS, Tamir ,  LYAKHOV, Alexander ,  GENDLER, Alexander ,  SISTLA, Krishnakanth ,  VARMA, Ankush ,  RAYESS, Rachid ,  ANGEL, Nimrod

IPC分类号： H02M3/156

公开(公告)号：EP3948553A1

公开(公告)日：2022-02-09

申请号：EP20778857.1

申请日：2020-03-04

申请人： INTEL Corporation

发明人： SINGH, Tejpal ,  HILEWITZ, Yedidya ,  VARMA, Ankush ,  LIU, Yen-Cheng ,  SISTLA, Krishnakanth V. ,  CHAMBERLAIN, Jeffrey

IPC分类号： G06F13/12 ,  G06F1/26 ,  G06F15/78

公开(公告)号：EP3881181A1

公开(公告)日：2021-09-22

申请号：EP19885784.9

申请日：2019-10-18

申请人： INTEL Corporation

发明人： RAGLAND, Daniel J. ,  THERIEN, Guy M. ,  VARMA, Ankush ,  DEHAEMER, Eric J. ,  MAYO, David T. ,  GUR, Ariel ,  BEN-RAPHAEL, Yoav ,  SECONI, Mark P.

IPC分类号： G06F9/52 ,  G06F13/20 ,  G06F1/28 ,  G06F9/50

公开(公告)号：EP4217823A1

公开(公告)日：2023-08-02

申请号：EP21873565.2

申请日：2021-09-24

申请人： INTEL Corporation

发明人： GARG, Vivek ,  VARMA, Ankush ,  SISTLA, Krishnakanth ,  GUPTA, Nikhil ,  BALIGAR, Nikethan Shivanand ,  WANG, Stephen ,  PALIT, Nilanjan ,  KAM, Timothy ,  PURANDARE, Adwait ,  GUPTA, Ujjwal ,  CHEN, Stanley ,  SHAPIRA, Dorit ,  VENUGOPAL, Shruthi ,  CHEMUDUPATI, Suresh ,  PARIKH, Rupal ,  DEHAEMER, Eric ,  SAMPATH, Pavithra ,  KANDULA, Phani Kumar ,  BANSAL, Yogesh ,  MULLA, Dean ,  TULANOWSKI, Michael ,  HAAKE, Stephen ,  HERDRICH, Andrew ,  DAS, Ripan

IPC分类号： G06F1/3203 ,  G06F1/30 ,  G06F1/26 ,  G06F9/50

公开(公告)号：EP4109217A2

公开(公告)日：2022-12-28

申请号：EP22161848.1

申请日：2022-03-14

申请人： Intel Corporation

发明人： PURANDARE, Adwait ,  STEINER, Ian ,  CHEN, Stanley ,  GUPTA, Nikhil ,  SRINIVASAN, Vasudevan ,  VARMA, Ankush

IPC分类号： G06F1/3203

摘要： In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.

公开(公告)号：EP3523727A1

公开(公告)日：2019-08-14

申请号：EP17859991.6

申请日：2017-10-10

申请人： Intel Corporation

发明人： NASSIF, Nevine ,  LIU, Yen-Cheng ,  SISTLA, Krishnakanth V. ,  PASDAST, Gerald ,  EACHEMPATI, Siva Soumya ,  SINGH, Tejpal ,  VARMA, Ankush ,  KUMASHIKAR, Mahesh K. ,  NIMMAGADDA, Srikanth ,  MOLNAR, Carleton L. ,  GEETHA, Vedaraman ,  CHAMBERLAIN, Jeffrey D. ,  HALLECK, William R. ,  CHRYSOS, George Z. ,  AYERS, John R. ,  SUBBAREDDY, Dheeraj R.

IPC分类号： G06F13/40

公开(公告)号：EP3259652A1

公开(公告)日：2017-12-27

申请号：EP16752781.1

申请日：2016-01-27

申请人： Intel Corporation

发明人： VARMA, Ankush ,  SISTLA, Krishnakanth V. ,  SRINIVASAN, Vasudevan ,  GORBATOV, Eugene ,  HENROID, Andrew D. ,  COOPER, Barnes ,  BROWNING, David W. ,  THERIEN, Guy M. ,  SONGER, Neil W. ,  HERMERDING II, James G.

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3206 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/50 ,  Y02B70/126 ,  Y02D10/171

摘要： In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.