公开(公告)号：EP4141912A1

公开(公告)日：2023-03-01

申请号：EP22182774.4

申请日：2022-07-04

申请人： INTEL Corporation

发明人： Wei, Andy

IPC分类号： H01L21/336 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/40 ,  B82Y10/00

摘要： Techniques are provided herein to form semiconductor devices having gate tie-down structures between the device gate and a buried/backside power rail (BPR). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure on a semiconductor region. The semiconductor region can be, for example, a fin or a set of one or more nanowires or nanoribbons that extends between a source region and a drain region. A BPR structure is beneath a dielectric layer that is between the BPR structure and the conductive material of the gate structure. A portion of the conductive material also extends through the dielectric material to provide a conductive via between the gate structure and the underlying BPR structure. The conductive material may be, for example, work function and/or metal fill material of the gate electrode of the gate structure.

公开(公告)号：EP4125117A1

公开(公告)日：2023-02-01

申请号：EP22159400.5

申请日：2022-03-01

申请人： Intel Corporation

发明人： Wei, Andy ,  Cheng, Yang-Chun ,  Chowdhury, Shaestagir ,  Bouche, Guillaume

IPC分类号： H01L21/74 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H01L21/8238

摘要： Techniques to form self-aligned lateral contacts. In an example, a first trench contact contacts a source or drain region of a transistor. A second trench contact includes non-contiguous first and second portions, each portion having a top surface that is co-planar with a top surface of the first trench contact as well as a top surface of the gate structure. A sidewall of the second trench contact is self-aligned to, and interfaces with, a sidewall of the first trench contact. A via extends from the first portion of the second trench contact to an underlying power rail. In some cases, the second portion of the second trench contact extends over a source or drain region of another transistor, without contacting that source or drain region. The fly-over portion of the second trench contact has a maximum height that is shorter than a maximum height of the first trench contact.

公开(公告)号：EP4138117A1

公开(公告)日：2023-02-22

申请号：EP22182715.7

申请日：2022-07-04

申请人： Intel Corporation

发明人： Wei, Andy ,  Bouche, Guillaume

IPC分类号： H01L21/336 ,  H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L29/78 ,  H01L29/16 ,  B82Y10/00

摘要： Techniques are provided to form semiconductor devices having a multi-layer spacer structure. In an example, a semiconductor device includes a semiconductor region extending between a source region and a drain region, and a gate layer extending over the semiconductor region. A spacer structure made up of one or more dielectric layers is present along a sidewall of the gate structure and along a sidewall of the source region or the drain region. The spacer structure has three different portions: a first portion along the sidewall of the gate, a second portion along the sidewall of the source or drain region, and a third portion that connects between the first two portions. The third portion of the spacer structure has a multi-layer configuration while the first and second portions have a fewer number of material layers.

公开(公告)号：EP4016599A1

公开(公告)日：2022-06-22

申请号：EP21195724.6

申请日：2021-09-09

申请人： Intel Corporation

发明人： Wei, Andy ,  Park, Changyok ,  Bouche, Guillaume ,  Ryu, Hyuk ,  Wallace, Charles ,  Haran, Mohit

IPC分类号： H01L21/768

摘要： Disclosed herein are transistor arrangements with trench contacts that have two parts - a first trench contact and a second trench contact - stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.