-
公开(公告)号：EP0185156B1
公开(公告)日：1991-12-18
申请号：EP85112609.4
申请日：1985-10-04
IPC分类号： G11C11/416
CPC分类号： G11C11/416
-
公开(公告)号：EP0454328A1
公开(公告)日：1991-10-30
申请号：EP91303250.4
申请日：1991-04-12
IPC分类号： H01L23/38
CPC分类号： H01L23/38 , H01L2224/16225 , Y10S257/93
摘要： A thermoelectrically cooled package (10) for housing an electronic component is provided. In a preferred form of the invention the electronic component is an integrated circuit chip (12) and the package includes a thermally conductive dielectric substrate (14), an input connecting portion and an output connecting portion (16) supported by the dielectric substrate, and the integrated circuit chip includes an input terminal and output terminal (18). The input terminal is electrically connected to the input connecting portion via a first conductive material, and the output terminal is electrically connected to the output connecting portion via a second conductive material (24). The first conductive material and the second conductive material thermoelectrically cool the integrated circuit chip when a signal passes through the first conductive material and the second conductive material.
摘要翻译： 提供一种用于容纳电子部件的热电冷却封装（10）。 在本发明的优选形式中，电子部件是集成电路芯片（12），并且封装包括导热电介质基板（14），输入连接部分和由电介质基板支撑的输出连接部分（16），以及 集成电路芯片包括输入端子和输出端子（18）。 输入端经由第一导电材料电连接到输入连接部分，并且输出端经由第二导电材料（24）电连接到输出连接部分。 当信号通过第一导电材料和第二导电材料时，第一导电材料和第二导电材料对集成电路芯片进行热电冷却。
-
公开(公告)号：EP0185978A3
公开(公告)日：1989-02-08
申请号：EP85115320.5
申请日：1985-12-03
IPC分类号： G11C11/40
CPC分类号： G11C11/416 , G11C11/4113
摘要： In an integrated circuit a random access read/write memory array, said memory array with m pairs of bit lines, each pair of bit lines including a first bit line and a second bit line; n pairs of word-drain lines, each pair of word-drain lines including a word line and a drain line; each of said m columns of memory cells being connected between the first bit line and the second bit line of a discret one of said m pairs of bit lines; each of said n rows of memory cells being connected between the word line and drain line of a discrete one of said n pairs of word-drain lines; controllable read/wr i te address decoder circuit means for reading the binary bit ("0" or"1") stored in any predetermined one of said m x n array of memory cells, or writing a binary bit ("0" or "1") in any predetermined one said m x n array of memory cells; and with n identical write enhancement circuit means for enhancing the operation of said random access read/write memory, each of said n identical write enhancement circuit means being a two-terminal device and each of said n identical circuit means being connected between the word line and the drain of a discrete one of said n pairs of word-drain lines.
摘要翻译： 在集成电路中，一个随机存取读/写存储器阵列，所述存储器阵列具有m对位线，每对位线包括第一位线和第二位线; n对字 - 漏极线，每对字 - 漏极线包括字线和漏极线; 所述m列存储器单元中的每一个连接在所述m对位线中的一个离散的一个的第一位线和第二位线之间; 所述n行存储器单元中的每一行连接在所述n对字线 - 漏极线中离散的一个的字线和漏极线之间; （“0”或“1”）的二进制位（“0”或“1”）的可控读/写地址解码器电路装置，用于读取存储在所述mxn存储器单元阵列中任何预定的一个中的二进制位 任何预定的一个所述m×n个存储单元阵列; 以及用于增强所述随机存取读/写存储器的操作的n个相同的写入增强电路装置，所述n个相同的写入增强电路装置中的每一个是双端装置，并且所述n个相同电路装置中的每一个连接在所述字线 以及所述n对字排线中的一个离散字线的漏极。
-
公开(公告)号：EP0185978A2
公开(公告)日：1986-07-02
申请号：EP85115320.5
申请日：1985-12-03
IPC分类号： G11C11/40
CPC分类号： G11C11/416 , G11C11/4113
摘要： In an integrated circuit a random access read/write memory array, said memory array with m pairs of bit lines, each pair of bit lines including a first bit line and a second bit line; n pairs of word-drain lines, each pair of word-drain lines including a word line and a drain line; each of said m columns of memory cells being connected between the first bit line and the second bit line of a discret one of said m pairs of bit lines; each of said n rows of memory cells being connected between the word line and drain line of a discrete one of said n pairs of word-drain lines; controllable read/wr i te address decoder circuit means for reading the binary bit ("0" or"1") stored in any predetermined one of said m x n array of memory cells, or writing a binary bit ("0" or "1") in any predetermined one said m x n array of memory cells; and with n identical write enhancement circuit means for enhancing the operation of said random access read/write memory, each of said n identical write enhancement circuit means being a two-terminal device and each of said n identical circuit means being connected between the word line and the drain of a discrete one of said n pairs of word-drain lines.
摘要翻译： 在集成电路中，随机存取读/写存储器阵列，具有m对位线的所述存储器阵列，每对位线包括第一位线和第二位线; n对字漏线，每对字漏线包括字线和漏极线; 所述m列存储器单元中的每一个连接在所述m对位线之一的离散器的第一位线和第二位线之间; 所述n行存储器单元中的每一个连接在所述n对字排泄线之间的离散的一对之间的字线和漏极线之间; 可读/写地址解码器电路装置，用于读取存储在所述存储器单元的任何预定的一个存储单元中的二进制位（“0”或“1”），或将二进制位（“0”或“1”）写入 任何预定的一个所述mxn阵列的存储单元; 并且具有用于增强所述随机存取读/写存储器的操作的n个相同写增强电路装置，所述n个相同写增强电路装置中的每一个是两端装置，并且所述n个相同电路装置中的每一个连接在字线 以及所述n对字排泄线中的离散的一对的漏极。
-
5.发明公开Integrated package having a thermoelectric cooler 失效Integrierte Packung mit einem thermoelektrischenKühler。
公开(公告)号：EP0447020A1
公开(公告)日：1991-09-18
申请号：EP91300420.6
申请日：1991-01-18
发明人： Mansuria, Mohanlal S. , Mosley, Joseph M. , Musa, Richard D. , Shutler, William F. , Tuozzolo, Vito J.
IPC分类号： H01L23/38
CPC分类号： H01L23/38 , H01L2224/16225 , H01L2224/48091 , H01L2924/15174 , Y10S257/93 , H01L2924/00014
摘要： A thermoelectrically cooled integrated circuit package (10) including an insulative module (12) which defines a cavity (14), a thermoelectric cooler (20) within the cavity, and an integrated circuit chip (16) connected to the thermoelectric cooler, thus providing an integrated circuit package in which the integrated circuit package itself dissipates thermal energy generated by the integrated circuit chip.
摘要翻译： 一种包括限定空腔的绝缘模块（12），所述空腔内的热电冷却器（20）和连接到所述热电冷却器的集成电路芯片（16）的热电冷却集成电路封装（10），由此提供 集成电路封装，其中集成电路封装本身散发由集成电路芯片产生的热能。
-
公开(公告)号：EP0185156A3
公开(公告)日：1989-02-08
申请号：EP85112609.4
申请日：1985-10-04
IPC分类号： G11C11/416
CPC分类号： G11C11/416
摘要： A bipolar random access memory array including "end of write shut down circuit means" coupled to the write circuit means is disclosed. The "end of write shut down circuit means" is activated by and only functions as the written cell switches state. The "end of write circuit means" is coupled between the opposite bit line (BL or BR) and preferably the write transistor of a write circuit of the write circuit means. The use of "the end of write circuit means" improves the overall operation of the memory and in particular the write operation thereof.
-
公开(公告)号：EP0185156A2
公开(公告)日：1986-06-25
申请号：EP85112609.4
申请日：1985-10-04
IPC分类号： G11C11/416
CPC分类号： G11C11/416
摘要： A bipolar random access memory array including "end of write shut down circuit means" coupled to the write circuit means is disclosed. The "end of write shut down circuit means" is activated by and only functions as the written cell switches state. The "end of write circuit means" is coupled between the opposite bit line (BL or BR) and preferably the write transistor of a write circuit of the write circuit means. The use of "the end of write circuit means" improves the overall operation of the memory and in particular the write operation thereof.
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.01 秒)
