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公开(公告)号：EP0713609A1
公开(公告)日：1996-05-29
申请号：EP94925876.0
申请日：1994-08-12
CPC分类号： H01L25/18 , H01L25/0657 , H01L2224/48091 , H01L2224/48145 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06582 , H01L2924/01057 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/16152 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012
摘要： An electronic package (20) is disclosed in which a plurality of stack IC (30) is designed to substitute for a single higher capacity IC chip, and fit into a host computer system, in such a way that the system is 'unaware' that the substition has been made. Memory packages are of primary interest. In order to 'translate' signals between the host system and the stacked IC memory chips, it is necessary to include suitable interface circuitry (140) between the host system and the stacked chips (30). Specific examples are disclosed of a 4 MEG SRAM package containing 4 stacked IC chips each supplying a 1 MEG memory, and of 64 MEG DRAM packages containing 4 stacked IC chips each supplying a 16 MEG memory. The interface circuitry (140) can be provided by a single special purpose IC chip included in the stack, which chip provides both buffering and decoding circuitry.
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公开(公告)号：EP0713609B1
公开(公告)日：2003-05-07
申请号：EP94925876.8
申请日：1994-08-12
IPC分类号： H01L25/00 , H01L27/00 , H01L25/065
CPC分类号： H01L25/18 , H01L25/0657 , H01L2224/48091 , H01L2224/48145 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06582 , H01L2924/01057 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/16152 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012
摘要： An electronic package (20) is disclosed in which a plurality of stack IC (30) is designed to substitute for a single higher capacity IC chip, and fit into a host computer system, in such a way that the system is 'unaware' that the substition has been made. Memory packages are of primary interest. In order to 'translate' signals between the host system and the stacked IC memory chips, it is necessary to include suitable interface circuitry (140) between the host system and the stacked chips (30). Specific examples are disclosed of a 4 MEG SRAM package containing 4 stacked IC chips each supplying a 1 MEG memory, and of 64 MEG DRAM packages containing 4 stacked IC chips each supplying a 16 MEG memory. The interface circuitry (140) can be provided by a single special purpose IC chip included in the stack, which chip provides both buffering and decoding circuitry.
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