公开(公告)号：EP4345825A1

公开(公告)日：2024-04-03

申请号：EP22198979.1

申请日：2022-09-30

申请人： Imec VZW

发明人： Verreck, Devin ,  Rosmeulen, Maarten

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08

摘要： This disclosure is concerned with NAND flash memory, and proposes a method for programming the NAND flash memory. The NAND flash memory comprises a semiconductor channel layer, a first gate on a first side of the channel layer, and a plurality of second gates on a second side of the channel layer. Each second gate is associated with one memory cell and connected to one word line. The method comprises applying a first voltage to the first gate, and a pass voltage to one or more word lines, to allow charge to inject into the channel layer and form charge packets. Each charge packet is arranged next to one of the second gates. The method further comprises applying a programming voltage to the word lines, to move the charge packets from the channel layer into the memory cells associated with the second gates next to which they are arranged.

公开(公告)号：EP4020471A1

公开(公告)日：2022-06-29

申请号：EP20217355.5

申请日：2020-12-28

申请人： Imec VZW

发明人： Keulemans, Grim ,  Rochus, Veronique ,  Rosmeulen, Maarten ,  Rottenberg, Xavier

IPC分类号： G11B15/18 ,  G11B15/20 ,  G11B15/40 ,  G11B23/04 ,  H02N1/00

摘要： The disclosure relates to a storage devices (10) configured to store data on a tape (11). The storage device (10) comprises the tape (11), which is configured to store data, and a data head (14), which is configured to read and/or write data from and/or to the tape (11). The storage device (10) further comprises an actuator (15) configured to move the tape (11) in a length direction in a step-wise manner. The actuator (15) comprises a number of pulling electrodes (16), wherein each pulling electrode (16) can be activated to exert a pulling force on the tape (11), and a number of clamping electrodes (17), wherein each clamping electrode (17) can be activated to clamp the tape (11).

公开(公告)号：EP4231353A1

公开(公告)日：2023-08-23

申请号：EP22156961.9

申请日：2022-02-16

申请人： Imec VZW

发明人： Rosmeulen, Maarten ,  Lee, Jiwon ,  Kar, Gouri Sankar ,  Mahato, Swaraj Bandhu

IPC分类号： H01L27/105 ,  G11C19/28 ,  H01L29/423 ,  H01L29/765

摘要： This disclosure relates to a charge-coupled device (CCD) memory. The CCD memory is 3D integrated. The CCD memory comprises a gate stack with a plurality of gate layers and spacer layers alternatingly arranged one on the other, and with a plurality of semiconductor-based channels extending in the stack. The channels may be formed from a semiconductor oxide material. Further, the CCD memory comprises dielectric layers, wherein each dielectric layer is arranged between one of the channels and at least one of the gate layers. Each channel of the CCD memory forms, in combination with the gate layers and at least one of the dielectric layers, a string of charge storage capacitors, and each string of charge storage capacitors is operable as a CCD register. The CCD memory also comprises a readout layer, which comprises a plurality of readout stages configured to individually readout stored charge from each of the CCD registers.

公开(公告)号：EP2600389B1

公开(公告)日：2020-01-15

申请号：EP11191148.3

申请日：2011-11-29

申请人： IMEC VZW

发明人： Pham, Nga Phuong ,  Rosmeulen, Maarten ,  Vandevelde, Bart

IPC分类号： H01L33/00 ,  H01L21/18 ,  H01L33/32 ,  H01L33/12

公开(公告)号：EP2869331A1

公开(公告)日：2015-05-06

申请号：EP14189000.4

申请日：2014-10-15

申请人： IMEC VZW

发明人： Motsnyi, Vasyl ,  Dutta, Barundeb ,  Rosmeulen, Maarten

IPC分类号： H01L21/02

CPC分类号： H01L29/2003 ,  B24B37/042 ,  H01L21/02002 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/30625 ,  H01L29/201 ,  H01L33/0025 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32

摘要： The embodiments of the present invention disclose a silicon substrate with a group III-V material and a method for fabricating a group III-V material on a silicon substrate. The method involves providing a silicon substrate (101). A first layer (104) formed atop the silicon substrate (101), is subsequently patterned to expose the underlying silicon substrate (101). A group III-V material layer is formed over the patterned first layer (104) and also on the exposed silicon substrate (101). The group III-V material layer (103) is subjected to chemical mechanical polishing (CMP) to expose the first layer (103) resulting in the formation of a plurality of areas (106) suitable for growing a device layer on the silicon substrate (101).

摘要翻译： 本发明的实施例公开了用III-V族材料和用于在硅衬底的制造III-V族材料的方法的硅基板。 该方法包括提供一硅衬底（101）。 形成在硅衬底（101）的顶上的第一层（104）随后被图案化以暴露下面的硅衬底（101）。 A组III-V材料层被形成在所述图案化的第一层（104），因此在暴露的硅衬底（101）。 所述III-V族物质层（103）进行化学机械抛光（CMP），以暴露的区域（106）适于在所述硅衬底上生长的器件层中的多个的形成而产生的第一层（103）（ 101）。