公开(公告)号：EP4441776A1

公开(公告)日：2024-10-09

申请号：EP22851021.0

申请日：2022-12-23

申请人： AZUR SPACE Solar Power GmbH

发明人： NISHIKAWA, Atsushi

IPC分类号： H01L21/02

CPC分类号： H01L21/02381 ,  H01L21/02488 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02639

公开(公告)号：EP2634824B1

公开(公告)日：2018-12-12

申请号：EP11836604.6

申请日：2011-10-26

申请人： SK Siltron Co., Ltd. ,  Kumoh National Institute of Technology Industry-Academic Cooperation Foundation

发明人： AN, Sung Jin ,  LEE, Dong Gun ,  KIM, Seok Han

IPC分类号： H01L33/12

CPC分类号： H01L33/02 ,  B82Y40/00 ,  H01L21/02104 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02444 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02499 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/38 ,  H01L29/06 ,  H01L33/007 ,  H01L33/12 ,  H01L33/32 ,  Y10S977/734

摘要： According to the present invention, a method for manufacturing a compound semiconductor comprises: forming a graphene-derived material layer on either a first selected substrate or a first selected compound semiconductor layer; forming a second compound semiconductor layer of at least one layer on at least said graphene-derived material layer, and changing the graphene-derived material layer so as to separate said second compound semiconductor layer of at least one layer.

公开(公告)号：EP3379579A1

公开(公告)日：2018-09-26

申请号：EP18170424.8

申请日：2009-11-13

申请人： FUJITSU LIMITED

发明人： KONDO, Daiyu ,  SATO, Shintaro

IPC分类号： H01L29/778 ,  H01L29/786 ,  H01L23/532 ,  H01L21/336 ,  H01L29/16

CPC分类号： H01L29/66045 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/043 ,  H01L23/53276 ,  H01L29/1606 ,  H01L29/66015 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78684 ,  H01L29/78696 ,  H01L2924/0002 ,  Y10S977/734 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device, comprising: forming a catalyst film (11) over an insulator (1b); growing a graphene layer (12, 13) originating from the catalyst film (11); and forming a source electrode (4) and a drain electrode (4) in contact with the graphene layer (12, 13), over the insulator (1b); wherein the graphene layer is a first graphene layer (12) grown from the upper surface of the catalyst film (11) and a second graphene layer (13) is grown from the lower surface of the catalyst film (11).

公开(公告)号：EP2316139B1

公开(公告)日：2018-03-21

申请号：EP09803141.2

申请日：2009-07-29

申请人： SK Siltron Co., Ltd.

发明人： KIM, Yong Jin ,  LEE, Dong Kun ,  KIM, Doo Soo

IPC分类号： H01L33/12 ,  H01L33/38 ,  H01L21/02 ,  H01L33/00 ,  H01L21/308

CPC分类号： H01L33/12 ,  H01L21/0237 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/02581 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3081 ,  H01L33/007 ,  H01L33/382

摘要： Disclosed are a semiconductor device, a light emitting device, and a method of manufacturing the same. The semiconductor device includes a substrate, a plurality of rods aligned on the substrate, a metal layer disposed on the substrate between the rods, and a semiconductor layer disposed on and between the rods. Electrical and optical characteristics of the semiconductor device are improved due to the metal layer.

公开(公告)号：EP2822026B1

公开(公告)日：2018-03-14

申请号：EP13754726.1

申请日：2013-02-28

申请人： Kyocera Corporation

发明人： KITADA, Masanobu

IPC分类号： H01L21/20 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L27/1203 ,  H01L21/0242 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/2007 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78654

摘要： Provided is a composite substrate having a semiconductor layer wherein diffusion of a metal is suppressed. This composite substrate has: a single crystal supporting substrate composed of an insulating oxide; a semiconductor layer, which has one main surface overlapping the supporting substrate, and which is composed of a single crystal; and a polycrystalline or amorphous intermediate layer, which is positioned between the supporting substrate and the semiconductor layer, and which has, as a main component, an element constituting the supporting substrate or an element constituting the semiconductor layer, and in which the ratio of accessory components other than the main component is less than 1 mass %.

公开(公告)号：EP3248211A1

公开(公告)日：2017-11-29

申请号：EP15797674.7

申请日：2015-11-20

申请人： Robert Bosch GmbH

发明人： HEUCK, Friedjof ,  NAGEL, Sabine ,  ROHLFING, Franziska

IPC分类号： H01L21/02 ,  H01L29/66

CPC分类号： H01L21/02639 ,  B81C1/00373 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02527 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/0262

摘要： The invention relates to a method for creating a micro-electromechanical or semiconductor structure, comprising the following steps: providing an starting structure, the surface of which has at least sections consisting of silicon dioxide; providing a starting material, or a mixture of several starting materials, which release a mixture of carbon, silicon and chlorine in an LPCVD process; introducing the starting structure and the one, or the mixture of, starting material into the LPCVD process; and thereby separating a carbon layer on the sections of the starting structure consisting of silicon dioxide. The invention also relates to a micro-electromechanical or semiconductor structure which is produced according to the method.

公开(公告)号：EP2933825B1

公开(公告)日：2017-07-05

申请号：EP14199093.7

申请日：2014-12-19

申请人： Flosfia Inc.

发明人： Hitora, Toshimi ,  Oda, Masaya

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/24 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02488 ,  H01L21/02565 ,  H01L21/02576 ,  H01L21/02581 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02628 ,  H01L21/02631 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

摘要： Provided is a crystalline multilayer structure having good semiconductor properties. The crystalline multilayer structure includes a base substrate and a corundum-structured crystalline oxide semiconductor thin film disposed directly on the base substrate or with another layer therebetween. The crystalline oxide semiconductor thin film is 0.1 µm or less in a surface roughness (Ra).

摘要翻译： 提供了具有良好半导体性质的晶体多层结构。 晶体多层结构包括基础衬底和刚性结构的晶体氧化物半导体薄膜，刚玉结构的晶体氧化物半导体薄膜直接设置在基础衬底上或在其间具有另一层。 结晶氧化物半导体薄膜的表面粗糙度（Ra）为0.1μm以下。

公开(公告)号：EP3050077A4

公开(公告)日：2017-04-26

申请号：EP13894184

申请日：2013-09-27

申请人： INTEL CORP

发明人： DASGUPTA SANSAPTAK ,  THEN HAN WUI ,  SUNG SEUNG HOON ,  GARDNER SANAZ K ,  RADOSAVLJEVIC MARKO ,  CHU-KUNG BENJAMIN ,  CHAU ROBERT S

IPC分类号： H01L21/20

CPC分类号： H01L21/0243 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/3085 ,  H01L21/8258 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66477 ,  H01L29/7787

摘要： An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.

摘要翻译： 绝缘层共形地沉积在衬底上的沟槽中的多个台面结构上。 绝缘层填充台面结构外部的空间。 成核层沉积在台面结构上。 III-V材料层沉积在成核层上。 III-V材料层横向生长在绝缘层上。

公开(公告)号：EP3127142A1

公开(公告)日：2017-02-08

申请号：EP15712173.2

申请日：2015-03-27

申请人： STMicroelectronics SA

发明人： DUTARTRE, Didier ,  JAOUEN, Hervé

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/763 ,  H01L29/04

CPC分类号： H01L21/7624 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/763 ,  H01L29/04

摘要： Method for production of a semiconductor wafer suitable for the manufacture of an SOI substrate, comprising the following steps: - production, on the upper face (2) of a semiconductor support (1), of a first layer (4) of polycrystalline semiconductor; then - formation of an interface area (12) on the upper face (7) of said first layer (4), the interface area (12) having a structure distinct from the crystalline structure of said first layer (4); then - production on said interface area (12) of a second layer (14) of polycrystalline semiconductor.

摘要翻译： 适合于通过提供一种制造SOI基片的半导体晶片：制作在半导体载体的顶侧的多晶半导体的第一层; 然后在第一层的顶侧上的界面区形成，worin界面区域从第一层的晶体结构不同的结构; 然后生产多晶半导体的在界面区的第二层。

公开(公告)号：EP3120385A1

公开(公告)日：2017-01-25

申请号：EP14886535.5

申请日：2014-03-18

申请人： Intel Corporation

发明人： MUKHERJEE, Niloy ,  DOYLE, Brian S. ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko ,  PILLARISETTY, Ravi ,  THEN, Han Wui ,  RAO, Valluri R. ,  CHAU, Robert S.

IPC分类号： H01L29/04 ,  H01L21/763

CPC分类号： H01L21/02513 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02422 ,  H01L21/02428 ,  H01L21/02488 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02549 ,  H01L21/02551 ,  H01L21/02595 ,  H01L21/02631 ,  H01L21/02675 ,  H01L21/763 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/78603 ,  H01L29/78681

摘要： Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a polycrystalline semiconductor material, and a polycrystalline dielectric disposed between and adjacent to the flexible substrate and the polycrystalline semiconductor material. The polycrystalline semiconductor material may include a polycrystalline III-V material, a polycrystalline II-VI material or polycrystalline germanium. Other embodiments may be disclosed and/or claimed.

摘要翻译： 本文公开了半导体组件的实施例以及相关的集成电路器件和技术。 在一些实施例中，半导体组件可以包括柔性衬底，多晶半导体材料以及设置在柔性衬底和多晶半导体材料之间和之间的多晶电介质。 多晶半导体材料。 多晶半导体材料可以包括多晶III-V材料，多晶II-VI材料或多晶锗。 可以公开和/或要求保护其他实施例。