公开(公告)号：EP1336179A1

公开(公告)日：2003-08-20

申请号：EP01982142.0

申请日：2001-09-26

申请人： Infineon Technologies AG

发明人： BOEHM, Thomas ,  ROEHR, Thomas ,  HOENIGSCHMID, Heinz

IPC分类号： G11C11/16

CPC分类号： G11C11/16 ,  H01L27/222

摘要： The invention relates to an integrated magnetoresistive semiconductor memory system, in which n memory cells that comprise two magnetic layers (WML, HML), each separated by a thin dielectric barrier (TL), and associated word lines (WL) and bit lines (BL) that cross one another are vertically stacked in n layers (L1, L2, L3, L4). The system further comprises a decoding circuit for selecting one of the n memory layers (L1 - L4). Said decoding circuit, on both ends of a word line (WL) or a bit line (BL), is provided with one arrangement each that consists of n layer selecting transistors (N0 - N3, N4 - N7) for selecting one of the n memory layers (L1 - L4), and with a line selection transistor (P0, P1) for selecting the respective horizontal word line or bit line (WL or BL) on which a voltage (V) is to be impressed.

公开(公告)号：EP1336179B1

公开(公告)日：2005-04-13

申请号：EP01982142.0

申请日：2001-09-26

申请人： Infineon Technologies AG

发明人： BOEHM, Thomas ,  ROEHR, Thomas ,  HOENIGSCHMID, Heinz

IPC分类号： G11C11/16

CPC分类号： G11C11/16 ,  H01L27/222

摘要： The invention relates to an integrated magnetoresistive semiconductor memory system, in which n memory cells that comprise two magnetic layers (WML, HML), each separated by a thin dielectric barrier (TL), and associated word lines (WL) and bit lines (BL) that cross one another are vertically stacked in n layers (L1, L2, L3, L4). The system further comprises a decoding circuit for selecting one of the n memory layers (L1 - L4). Said decoding circuit, on both ends of a word line (WL) or a bit line (BL), is provided with one arrangement each that consists of n layer selecting transistors (N0 - N3, N4 - N7) for selecting one of the n memory layers (L1 - L4), and with a line selection transistor (P0, P1) for selecting the respective horizontal word line or bit line (WL or BL) on which a voltage (V) is to be impressed.

公开(公告)号：EP1342242B1

公开(公告)日：2004-06-09

申请号：EP01993931.3

申请日：2001-11-12

申请人： Infineon Technologies AG

发明人： BOEHM, Thomas ,  HÖNIGSCHMID, Heinz ,  RÖHR, Thomas

IPC分类号： G11C11/16

CPC分类号： G11C11/16

摘要： The invention relates to an MRAM arrangement, comprising a selection transistor (T), connected to several MTJ memory cells (1) and with an increased channel width.

公开(公告)号：EP1342242A2

公开(公告)日：2003-09-10

申请号：EP01993931.3

申请日：2001-11-12

申请人： Infineon Technologies AG

发明人： BOEHM, Thomas ,  HÖNIGSCHMID, Heinz ,  RÖHR, Thomas

IPC分类号： G11C11/16

CPC分类号： G11C11/16

摘要： The invention relates to an MRAM arrangement, comprising a selection transistor (T), connected to several MTJ memory cells (1) and with an increased channel width.