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公开(公告)号：EP1389336B1
公开(公告)日：2007-04-11
申请号：EP02750932.2
申请日：2002-05-15
IPC分类号： G11C29/00
摘要： The invention relates to a method for testing a data memory with an integrated test data compression circuit (16). Said data memory (1) comprises a memory cell field (10) having a plurality of addressable memory cells, a write/read amplifier (12) for writing and reading data into the memory cells by means of an internal data bus (12) of the data memory (1), and a test data compression circuit (16). Test data sequences which are respectively successively read out of the memory cell field (10) are compressed with stored reference test data sequences in order to respectively produce a display date which indicates whether at least one data error has occurred in the test data sequence which has been read out.
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公开(公告)号：EP1389336A1
公开(公告)日：2004-02-18
申请号：EP02750932.2
申请日：2002-05-15
IPC分类号： G11C29/00
摘要： The invention relates to a method for testing a data memory with an integrated test data compression circuit (16). Said data memory (1) comprises a memory cell field (10) having a plurality of addressable memory cells, a write/read amplifier (12) for writing and reading data into the memory cells by means of an internal data bus (12) of the data memory (1), and a test data compression circuit (16). Test data sequences which are respectively successively read out of the memory cell field (10) are compressed with stored reference test data sequences in order to respectively produce a display date which indicates whether at least one data error has occurred in the test data sequence which has been read out.
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