公开(公告)号：EP1671331B1

公开(公告)日：2007-07-11

申请号：EP04787565.3

申请日：2004-09-23

申请人： Innovative Silicon SA

发明人： FAZAN, Pierre ,  OKHONIN, Serguei

IPC分类号： G11C11/404

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： The present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State '0' in a memory cell employing an electrically floating body transistor). In this regard, the present invention programs a logic low or State '0' in the memory cell while the electrically floating body transistor is in the 'OFF' state or substantially 'OFF' state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

公开(公告)号：EP1716600A1

公开(公告)日：2006-11-02

申请号：EP05850314.5

申请日：2005-12-21

申请人： Innovative Silicon SA

发明人： OKHONIN, Serguei ,  NAGOGA, Mikhail

IPC分类号： H01L29/78 ,  H01L27/108 ,  G11C11/404

CPC分类号： G11C11/404 ,  G11C11/4076 ,  G11C2211/4016 ,  H01L27/1023 ,  H01L27/108 ,  H01L29/78 ,  H01L29/7841

摘要： A technique of sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one embodiment, the present inventions are directed to a memory cell, having an electrically floating body transistor, and/or a technique of reading the data state in such a memory cell. In this regard, the present inventions employ the intrinsic bipolar transistor current to read and/or determine the data state of the electrically floating body memory cell (for example, whether the electrically floating body memory cell is programmed in a State '0' and State ''I'). During the read operation, the data state is determined primarily by or sensed substantially using the bipolar current responsive to the read control signals and significantly less by the interface channel current component, which is negligible relatively to the bipolar component. The bipolar transistor current may be very sensitive to the floating body potential due to the high gain of the intrinsic bipolar transistor. As such, the programming window obtainable with the bipolar reading technique may be considerably higher (for example, up two orders of magnitude higher) than the programming window employing a conventional reading technique (which is based primarily on the interface channel current component.

公开(公告)号：EP1671331A2

公开(公告)日：2006-06-21

申请号：EP04787565.3

申请日：2004-09-23

申请人： Innovative Silicon SA

发明人： FAZAN, Pierre ,  OKHONIN, Serguei

IPC分类号： G11C11/404

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： The present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State '0' in a memory cell employing an electrically floating body transistor). In this regard, the present invention programs a logic low or State '0' in the memory cell while the electrically floating body transistor is in the 'OFF' state or substantially 'OFF' state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

公开(公告)号：EP1987520A2

公开(公告)日：2008-11-05

申请号：EP07750961.0

申请日：2007-02-15

申请人： Innovative Silicon SA

发明人： CARMAN, Eric ,  OKHONIN, Serguei ,  JONES, Mark-Eric

IPC分类号： G11C11/34

CPC分类号： H01L29/7841 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/404 ,  G11C11/565 ,  G11C2211/4016

摘要： Multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc ) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory)

公开(公告)号：EP1924997A1

公开(公告)日：2008-05-28

申请号：EP06777170.9

申请日：2006-09-06

申请人： Innovative Silicon SA

发明人： OKHONIN, Serguei ,  NAGOGA, Mikhail

IPC分类号： G11C11/404 ,  G11C11/4076

CPC分类号： G11C11/409 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/4076 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7841

摘要： A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the present inventions may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.

公开(公告)号：EP1405314A2

公开(公告)日：2004-04-07

申请号：EP02745383.6

申请日：2002-06-05

申请人： Innovative Silicon SA ,  Ecole Polytechnique Fédérale de Lausanne (EPFL)

发明人： FAZAN, Pierre, Christophe ,  OKHONIN, Serguei

IPC分类号： G11C11/404 ,  G11C11/403 ,  H01L27/108

CPC分类号： H01L27/108 ,  G11C11/403 ,  G11C11/404 ,  G11C11/5621 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841 ,  H04N5/3355 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gate 28, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body 22 can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate 28 and the drain 22 and between the source 18 and the drain 22.

摘要翻译： 公开了一种半导体器件，例如存储器件或辐射检测器，其中数据存储单元形成在衬底13上。每个数据存储单元包括具有源极18，漏极22和栅极28的场效应晶体管， 以及布置在源极和漏极之间用于存储体内产生的电荷的主体。 可以通过施加到晶体管的输入信号来调节主体22中的净电荷的大小，并且可以通过在栅极28与栅极28之间施加电压信号来至少部分地抵消输入信号对净电荷的调节 漏极22以及源极18和漏极22之间。