公开(公告)号：EP3394729A1

公开(公告)日：2018-10-31

申请号：EP16879791.8

申请日：2016-11-23

申请人： Intel Corporation

发明人： ANDERSON, Cristina S. ,  CORNEA-HASEGAN, Marius A. ,  OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  CORBAL, Jesus ,  ASTAFEV, Nikita ,  CHARNEY, Mark J. ,  GIRKAR, Milind B. ,  GRADSTEIN, Amit ,  RUBANOVICH, Simon ,  SPERBER, Zeev

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F7/4876 ,  G06F7/485 ,  G06F7/49915

摘要： An example processor includes a register and a fused multiply-add (FMA) low functional unit. The register stores first, second, and third floating point (FP) values. The FMA low functional unit receives a request to perform an FMA low operation: multiplies the first FP value with the second FP value to obtain a first product value; adds the first product with the third FP value to generate a first result value; rounds the first result to generate a first FMA value; multiplies the first FP value with the second FP value to obtain a second product value; adds the second product value with the third FP value to generate a second result value; and subtracts the FMA value from the second result value to obtain a third result value, which can then be normalized and rounded (FMA low result) and sent the FMA low result to an application.

公开(公告)号：EP3394730A1

公开(公告)日：2018-10-31

申请号：EP16879792.6

申请日：2016-11-23

申请人： Intel Corporation

发明人： ANDERSON, Cristina S. ,  CORNEA-HASEGAN, Marius A. ,  OULD-AHMED-VALL, Elmoustapha ,  VALENTINE, Robert ,  CORBAL, Jesus ,  ASTAFEV, Nikita ,  CHARNEY, Mark J. ,  GIRKAR, Milind B. ,  GRADSTEIN, Amit ,  RUBANOVICH, Simon ,  SPERBER, Zeev

IPC分类号： G06F9/30

CPC分类号： G06F7/485

摘要： An example processor includes a register and an ADD low functional unit. The register stores first, second, and third floating point (FP) values. The ADD low functional unit receives a request to perform an ADD low operation and, responsive to the request: adds the first FP value with the second FP value to obtain a first sum value; rounds the first sum value to generate an ADD value; adds the first FP value with the second FP value to obtain a second sum value; subtracts the ADD value from the second sum value to generate a difference value; normalizes the difference value to obtain a normalized difference value; rounds the normalized difference value to generate an ADD low value; and sends the ADD low value to an application.