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118 条记录 (耗时 0.016 秒)

    Floating-point adder circuitry
    1.
    发明公开
    Floating-point adder circuitry 有权
    Gleitkomma-Addierer-Schaltung

    公开(公告)号：EP2846257A1

    公开(公告)日：2015-03-11

    申请号：EP14182740.2

    申请日：2014-08-29

    申请人： Altera Corporation

    发明人： Czajkowski, Tomasz

    IPC分类号： G06F7/485 ,  G06F7/499

    CPC分类号： G06F7/485 ,  G06F5/012 ,  G06F7/49915 ,  G06F17/10 ,  G06F2207/483

    摘要： An integrated circuit is provided that performs floating-point addition or subtraction operations involving at least three floating-point numbers. The floating-point numbers are pre-processed by dynamically extending the number of mantissa bits, determining the floating-point number with the biggest exponent, and shifting the mantissa of the other floating-point numbers to the right. Each extended mantissa has at least twice the number of bits of the mantissa entering the floating-point operation. The exact bit extension is dependent on the number of floating-point numbers to be added. The mantissas of all floating-point numbers with an exponent smaller than the biggest exponent are shifted to the right. The number of right shift bits is dependent on the difference between the biggest exponent and the respective floating-point exponent.

    摘要翻译： 提供一种集成电路，其执行涉及至少三个浮点数的浮点加法或减法运算。 通过动态扩展尾数位数，以最大指数确定浮点数，并将其他浮点数的尾数向右移动，对浮点数进行预处理。 每个扩展尾数具有进入浮点运算的尾数的位数的至少两倍。 精确的位扩展取决于要添加的浮点数的数量。 指数小于最大指数的所有浮点数的尾数向右移动。 右移位的数量取决于最大指数和相应浮点指数之间的差异。

    MODAL INTERVAL PROCESSOR
    3.
    发明公开
    MODAL INTERVAL PROCESSOR 审中-公开
    模态间隔处理器

    公开(公告)号：EP1872201A2

    公开(公告)日：2008-01-02

    申请号：EP06740509.2

    申请日：2006-04-05

    申请人： Sunfish Studio, LLC

    发明人： HAYES, Nathan, T.

    IPC分类号： G06F7/38

    CPC分类号： G06F7/485 ,  G06F7/49989 ,  G06F2207/483

    摘要： A logic circuit computes various modal interval arithmetic values using a plurality of arithmetic function units (20). A multiplexer (68) gates the desired arithmetic values to a storage register (43).

    摘要翻译： 逻辑电路使用多个算术函数单元（20）来计算各种模态间隔运算值。 多路复用器（68）将期望的算术值选通到存储寄存器（43）。

    Elimination of rounding step in the short path of a floating point adder
    4.
    发明公开
    Elimination of rounding step in the short path of a floating point adder 审中-公开
    消除叛乱罪

    公开(公告)号：EP1282034A2

    公开(公告)日：2003-02-05

    申请号：EP02015111.4

    申请日：2002-07-05

    申请人： FUJITSU LIMITED

    发明人： Naini, Ajay ,  Dhablania, Atul ,  James, Warren

    IPC分类号： G06F7/50

    CPC分类号： G06F7/485 ,  G06F7/49947 ,  G06F7/49957 ,  G06F2207/3868

    摘要： The apparatus and method of the present invention operates to perform a floating-point operation involving at least two operands in floating-point representation. The apparatus comprises two concurrent data paths, a short path and a long path. The short path is used to produce a result of the floating-point operation if the floating-point operation is a subtract operation and the exponent difference of the two operands is 0, or if the floating-point operation is a subtract operation, the exponent difference is 1, and the mantissa of the operand with a larger exponent is within a predetermined number range. The long path is used to produce a result of the floating-point operation if the floating point operation is an addition operation, or if it is a subtraction operation and the exponent difference is larger than one, or if it is a subtract operation, the exponent difference is 1, and the mantissa of the operand with the larger exponent is within another predetermined number range. Using this logic for selecting a data path for the floating-point operation, the short path does not require means such as an incrementer for post subtraction normalization.

    摘要翻译： 本发明的装置和方法用于执行涉及浮点表示中至少两个操作数的浮点运算。 该装置包括两条并行数据路径，一条短路径和一条长路径。 如果浮点运算是减法运算，并且两个运算数的指数差为0，则使用短路来产生浮点运算的结果，或者浮点运算是减法运算，则指数 差为1，具有较大指数的操作数的尾数在预定数量范围内。 如果浮点运算是加法运算，或者是减法运算，并且指数差大于1，或者减法运算，则长路径用于产生浮点运算的结果， 指数差为1，具有较大指数的操作数的尾数在另一预定数范围内。 使用该逻辑来选择用于浮点运算的数据路径，短路径不需要诸如用于后减法归一化的递增器的装置。

    Result normalizer and method of operation
    7.
    发明公开
    Result normalizer and method of operation 失效
    结果其运作正规化和方法。

    公开(公告)号：EP0657805A1

    公开(公告)日：1995-06-14

    申请号：EP94309074.6

    申请日：1994-12-06

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  MOTOROLA INC.

    发明人： Burgess, Bradley G. ,  Elliott, Timothy A. ,  Olson, Christopher H. ,  Potter, Terence M.

    IPC分类号： G06F7/50 ,  G06F5/01

    CPC分类号： G06F7/485 ,  G06F5/012

    摘要： A result normalizer (58) for use with an adder (56) generates a mask in two stages that indicates the location of the leading one in the adder result. In the first stage, a leading zero anticipator (68) determines the position to within two digits. In the second stage, a count leading zero indicator (70) determines the position to a single digit. The mask is used to control the number of digits that each stage of a multiplexer array (66) shifts the adder result. The output of the multiplexer array thereby contains a leading one. The result normalizer may be advantageously used in high performance applications such as in a floating point execution unit in a data processor or in digital signal processing systems.

    Method and apparatus for computing floating point data
    9.
    发明公开
    Method and apparatus for computing floating point data 失效
    计算浮点数据的方法和装置

    公开(公告)号：EP0472148A3

    公开(公告)日：1993-07-21

    申请号：EP91113901.2

    申请日：1991-08-20

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： Suzuki, Masato ,  Yasutome, Mikako ,  Tsuruta, Hideyo

    IPC分类号： G06F7/48 ,  G06F7/50 ,  G06F7/52

    CPC分类号： G06F7/485 ,  G06F7/483 ,  G06F7/4876 ,  G06F7/49936 ,  G06F7/49957

    摘要： A method and an apparatus for computing the floating point data which is used in a central processing unit and so on for a digital computer, and especially for effecting four fundamental rules of arithmetics of the floating point data and the rounding and the normalizing computation, and wherein at the case of the addition, subtraction, the mantissa portion of the two floating point data and the generated round addition values are added to an adder, and, at the case of the multiplication, the sum output and the carry output of the multiplying unit, and the generated round addition values are added to the adder so as to correct the least significant bit of the output of the adder or the round addition value is again added, whereby, in order to provide the necessity of reoperation for round becoming small, the average processing step numbers because small in comporison with the conventional, and, as the mantissa operation and round are practised by the same adder at the same time, the increasing of handwares are extreamly small.