公开(公告)号：EP4016316A1

公开(公告)日：2022-06-22

申请号：EP21198633.6

申请日：2021-09-23

申请人： Intel Corporation

发明人： MEHTA, Akanksha ,  GRANIELLO, Benjamin ,  MADDAH, Rakan ,  HILLIER, Philip ,  MANGOLD, Richard P. ,  DAMLE, Prashant S. ,  KHOCHARE, Kunal A.

IPC分类号： G06F13/16 ,  G11C7/10 ,  G11C13/00 ,  G11C16/34

摘要： A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array. In this way, the subsequent write commands received during a time window after the first write command are coalesced and a single subsequent write command is sent to the memory.

公开(公告)号：EP3859539A1

公开(公告)日：2021-08-04

申请号：EP20215672.5

申请日：2020-12-18

申请人： INTEL Corporation

发明人： QAWAMI, Shekoufeh ,  HILLIER, Philip ,  GRANIELLO, Benjamin ,  SUNDARAM, Rajesh

IPC分类号： G06F13/16 ,  G06F3/06

摘要： A memory system includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay. The system can select to perform memory access operations with the NV memory device with the asymmetry, in which case write operations have a lower delay than read operations. The system can alternatively select to perform memory access operations with the NV memory device where a configured write operation delay that matches the read operation delay.

公开(公告)号：EP3557426A3

公开(公告)日：2019-12-11

申请号：EP19161452.8

申请日：2019-03-07

申请人： INTEL Corporation

发明人： KUMAR, Karthik ,  GRANIELLO, Benjamin ,  SCHMISSEUR, Mark A. ,  WILLHALM, Thomas ,  GUIM BERNAT, Francesc

IPC分类号： G06F12/0888 ,  G06F12/0811 ,  G06F12/0897

摘要： A method is described. The method includes configuring different software programs that are to execute on a computer with customized hardware caching service levels. The available set of hardware caching levels at least comprise L1, L2 and L3 caching levels and at least one of the following hardware caching levels is available for customized support of a software program L2, L3 and L4.