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    THRESHOLD VOLTAGE EXPANSION
    6.
    发明公开
    THRESHOLD VOLTAGE EXPANSION 审中-公开
    门限电压扩展

    公开(公告)号：EP3180789A1

    公开(公告)日：2017-06-21

    申请号：EP15832126.5

    申请日：2015-06-04

    申请人： Intel Corporation

    发明人： PANDEY, Abhinav ,  BELGAL, Hanmant P. ,  DAMLE, Prashant S. ,  KRIPANIDHI, Arjun ,  URIBE, Sebastian T. ,  LY-GAGNON, Dany-Sebastien ,  RANGAN, Sanjay ,  PANGAL, Kiran

    IPC分类号： G11C16/34 ,  G11C16/10

    摘要： Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.

    摘要翻译： 本文描述了包括与扩展存储器单元的阈值电压窗口相关联的系统，方法和设备的实施例。 具体而言，在一些实施例中，存储器单元可以被配置为通过被设置为置位状态或复位状态来存储数据。 在一些实施例中，可以在读取过程之前在置位状态下的存储器单元上执行伪读取过程。 在一些实施例中，修改的重置算法可以在重置状态下的存储器单元上执行。 其他实施例可以被描述或要求保护。

    WRITE DISTURB REFRESH RATE REDUCTION USING WRITE HISTORY BUFFER
    8.
    发明公开
    WRITE DISTURB REFRESH RATE REDUCTION USING WRITE HISTORY BUFFER 审中-公开

    公开(公告)号：EP4016316A1

    公开(公告)日：2022-06-22

    申请号：EP21198633.6

    申请日：2021-09-23

    申请人： Intel Corporation

    发明人： MEHTA, Akanksha ,  GRANIELLO, Benjamin ,  MADDAH, Rakan ,  HILLIER, Philip ,  MANGOLD, Richard P. ,  DAMLE, Prashant S. ,  KHOCHARE, Kunal A.

    IPC分类号： G06F13/16 ,  G11C7/10 ,  G11C13/00 ,  G11C16/34

    摘要： A write history buffer can prevent write disturb in memory, enabling a reduction in write disturb refresh rate and improvement in performance. A memory device can include circuitry to cause consecutive write commands to the same address to be spaced by an amount of time to reduce incidences of write disturb, and therefore reduce the required write disturb refresh rate and improve performance. In one example, a memory device receives multiple write commands to an address. In response to receipt of the multiple write commands, the first write command is sent to the memory and a timer is started. Subsequent write commands that are received after the first write command and before expiration of the timer are held in a buffer. After expiration of the timer, only the most recent of the subsequent write commands to the address is sent to the memory array. In this way, the subsequent write commands received during a time window after the first write command are coalesced and a single subsequent write command is sent to the memory.