公开(公告)号：EP4203641A1

公开(公告)日：2023-06-28

申请号：EP22205746.5

申请日：2022-11-07

申请人： INTEL Corporation

发明人： ONG, Clifford ,  LAVRIC, Dan ,  GULER, Leonard ,  CHIU Yen Ting ,  SHRIDHARAN, Smita ,  GUO, Zheng ,  KARL, Eric A. ,  GHANI, Tahir

IPC分类号： H10B10/00 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

摘要： Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors (292) and pull-down transistors (291) having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.

公开(公告)号：EP3123473A1

公开(公告)日：2017-02-01

申请号：EP15768870.6

申请日：2015-03-03

申请人： Intel Corporation

发明人： KULKARNI, Jaydeep P. ,  THAPLOO, Anupama ,  RAJWANI, Iqbal ,  KOO, Kyung-Hoae ,  KARL, Eric A. ,  KHELLAH, Muhammad

IPC分类号： G11C7/10 ,  G11C7/06 ,  G11C8/08

CPC分类号： G11C7/12 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/419 ,  G11C17/16 ,  G11C2207/005

摘要： Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.

摘要翻译： 实施例包括与辅助电路有关的装置，方法和系统，该辅助电路可耦合到存储器系统的一个或多个部件，以选择性地降低传送到部件的电源电压。 例如，辅助电路可以耦合到多个比特单元（例如，寄存器文件比特单元）。 辅助电路可以在写入操作的至少一部分期间和/或在位单元的非活动状态期间选择性地降低传送到位单元的电源电压。 另外或替代地，辅助电路可以耦合到读取电路，以在读取电路的非活动状态期间选择性地降低传送到读取电路的电源电压。 辅助电路可以包括与主电源轨和位单元和/或读电路的供电节点之间的一个或多个二极管并联耦合的控制晶体管。