公开(公告)号：EP3902200A1

公开(公告)日：2021-10-27

申请号：EP21179870.7

申请日：2012-03-30

Applicant: INTEL Corporation

Inventor： YAP, Kirk S ,  WOLRICH, Gilbert M ,  GUILFORD, James D ,  GOPAL, Vinodh ,  OZTURK, Erdinc ,  GULLEY, Sean M ,  FEGHALI, Wajdi K ,  DIXON, Martin G

IPC: H04L9/32 ,  H04L9/06 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：EP3627764A1

公开(公告)日：2020-03-25

申请号：EP19205541.6

申请日：2012-03-30

Applicant: Intel Corporation

Inventor： YAP, Kirk S ,  WOLRICH, Gilbert M ,  GUILFORD, James D ,  GOPAL, Vinodh ,  OZTURK, Erdinc ,  GULLEY, Sean M ,  FEGHALI, Wajdi K ,  DIXON, Martin G

IPC: H04L9/32 ,  H04L9/06 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：EP2832036A1

公开(公告)日：2015-02-04

申请号：EP12873156.9

申请日：2012-03-30

Applicant: Intel Corporation

Inventor： YAP, Kirk S. ,  WOLRICH, Gilbert M. ,  GUILFORD, James D. ,  GOPAL, Vinodh ,  OZTURK, Erdinc ,  GULLEY, Sean M. ,  FEGHALI, Wajdi K. ,  DIXON, Martin G.

IPC: H04L9/28

CPC classification number: G06F9/3016 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/384 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F15/8007 ,  G06F21/602 ,  G06F2212/452 ,  G06F2212/68 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/125

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Abstract translation: 处理器包括指令解码器，用于接收处理安全散列算法2（SHA-2）散列算法的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储SHA-2状态和第二操作数 与第二存储位置相关联以存储多个消息和循环常数。 处理器还包括执行单元，其耦合到指令解码器，以在由第一操作数和由第二操作数指定的多个消息和循环常数指定的SHA-2状态上执行SHA-2散列算法的一个或多个迭代， 响应第一条指令。