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    SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    3.
    发明公开
    SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开

    公开(公告)号：EP3189617A4

    公开(公告)日：2018-05-02

    申请号：EP15837850

    申请日：2015-08-14

    Applicant: INTEL CORP

    Inventor： GUERON SHAY ,  KRASNOV VLAD

    IPC: H04L9/06 ,  G06F9/30

    CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/3895 ,  G09C1/00 ,  H04L2209/125

    Abstract: A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.

    RSA ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    4.
    发明公开
    RSA ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
    RSA-ALGORITHMUSBESCHLEUNIGUNGSPROZESSOREN，VERFAHREN，SYSTEME UND ANWEISUNGEN

    公开(公告)号：EP3087470A4

    公开(公告)日：2017-08-16

    申请号：EP13900536

    申请日：2013-12-28

    Applicant: INTEL CORP

    Inventor： LU YANG ,  SUN XIANGZHENG ,  QIAO NAN STAN

    IPC: G06F7/544 ,  G06F7/72 ,  G06F9/30

    CPC classification number: H04L9/302 ,  G06F7/722 ,  G06F7/723 ,  G06F9/30007 ,  G06F9/3017 ,  G06F9/3895

    Abstract: A processor includes a decode unit to decode an instruction. The instruction indicates a first 64-bit source operand having a first 64-bit value, indicates a second 64-bit source operand having a second 64-bit value, indicates a third 64-bit source operand having a third 64-bit value, and indicates a fourth 64-bit source operand having a fourth 64-bit value. An execution unit is coupled with the decode unit. The execution unit is operable, in response to the instruction, to store a result. The result includes the first 64-bit value multiplied by the second 64-bit value added to the third 64-bit value added to the fourth 64-bit value. The execution unit may store a 64-bit least significant half of the result in a first 64-bit destination operand indicated by the instruction, and store a 64-bit most significant half of the result in a second 64-bit destination operand indicated by the instruction.

    Abstract translation: 处理器包括解码单元以解码指令。 该指令指示具有第一个64位值的第一个64位源操作数，指示具有第二个64位值的第二个64位源操作数，指示具有第三个64位值的第三个64位源操作数， 并指示具有第四个64位值的第四个64位源操作数。 执行单元与解码单元耦合。 执行单元响应于该指令可操作地存储结果。 结果包括第一个64位值乘以第二个64位值加上第三个64位值加到第四个64位值。 执行单元可以将结果的64位最低有效一半存储在由指令指示的第一个64位目的操作数中，并将结果的64位最高有效一半存储在第二个64位目的操作数 指令。

    Memory interconnect network architecture for vector processor
    9.
    发明公开
    Memory interconnect network architecture for vector processor 审中-公开
    SpeekerverbindungsnetzwerkarchitekturfürVektorprozessor

    公开(公告)号：EP2725485A2

    公开(公告)日：2014-04-30

    申请号：EP13188947.9

    申请日：2013-10-16

    Applicant: Analog Devices Technology

    Inventor： Lerner, Boris ,  Perkins, Michael G. ,  Redford, John L.

    IPC: G06F9/30

    CPC classification number: G06F13/40 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/3824 ,  G06F9/3887 ,  G06F13/38 ,  G06F13/4022

    Abstract: The present disclosure provides a memory interconnection architecture for a processor, such as a vector processor, that performs parallel operations. An example processor may include a compute array that includes processing elements; a memory that includes memory banks; and a memory interconnect network architecture that interconnects the compute array to the memory. In an example, the memory interconnect network architecture includes a switch-based interconnect network and a non-switch based interconnect network. The processor is configured to synchronously load a first data operand to each of the processing elements via the switch-based interconnect network and a second data operand to each of the processing elements via the non-switch-based interconnect network.

    Abstract translation: 本公开提供了用于执行并行操作的诸如矢量处理器的处理器的存储器互连架构。 示例处理器可以包括包括处理元件的计算阵列; 包括记忆库的记忆; 以及将计算阵列与存储器互连的存储器互连网络架构。 在一个示例中，存储器互连网络架构包括基于交换机的互连网络和基于非交换机的互连网络。 处理器被配置为经由基于交换机的互连网络将第一数据操作数同步地加载到每个处理元件，并且经由非基于交换机的互连网络将第二数据操作数同时加载到每个处理元件。

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