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公开(公告)号：EP2798520A1
公开(公告)日：2014-11-05
申请号：EP11878906.4
申请日：2011-12-29
申请人： Intel Corporation
发明人： MAGKLIS, Grigorios , CODINA, Josep M. , ZILLES, Craig B. , NEILLY, Michael , SAMUDRALA, Sridhar , MARTINEZ VICENTE, Alejandro , XEKALAKIS, Polychronis , SANCHEZ, F. Jesus , LUPON, Marc , TOURNAVITIS, Georgios , GIBERT CODINA, Enric , GOMEZ REQUENA, Crispin , GONZALEZ, Antonio , HYUSEINOVA, Mirem , KOTSELIDIS, Christos E. , LATORRE, Fernando , LOPEZ, Pedro , MADRILES, Carlos , MARCUELLO, Pedro , MARTINEZ, Raul , ORTEGA, Daniel , PAVLOU, Demos , STAVROU, Kyriakos A.
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3842
摘要： Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction.
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公开(公告)号：EP3238045A1
公开(公告)日：2017-11-01
申请号：EP15873973.0
申请日：2015-11-23
申请人： Intel Corporation
发明人： OULD-AHMED-VALL, Elmoustapha , ESPASA, Roger , GUILLEN, David F. , SANCHEZ, F. Jesus , SOLE, Guillem
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30167 , G06F9/34
摘要： An apparatus and method are described for performing vector horizontal logical instruction. For example, one embodiment of a processor comprises: fetch logic to fetch an instruction from memory, and execution logic to determine a value of a first set of one or more data elements from a first specified set of bits of an immediate operand, wherein positions of the first set of one or more data elements determined from the first specified set of bits of the immediate operand are based on a first set of one or more index values that have a most significant bit corresponding to a packed data element at a first set of one or more positions of a destination packed data operand and that have a least significant bit corresponding to a data element at a corresponding position of a first source packed data operand.
摘要翻译： 描述了用于执行矢量水平逻辑指令的设备和方法。 例如，处理器的一个实施例包括：用于从存储器获取指令的提取逻辑，以及用于从立即数操作数的第一特定位集合中确定第一组一个或多个数据元素的值的执行逻辑，其中位置 根据所述立即数操作数的所述第一指定位集合确定的所述第一组一个或多个数据元素的第一集合是基于一个或多个索引值的第一集合，所述第一集合具有对应于第一集合中的打包数据元素的最高有效位 的目的地打包数据操作数的一个或多个位置并且具有对应于第一源打包数据操作数的对应位置处的数据元素的最低有效位。
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3.发明公开
公开(公告)号：EP3238041A1
公开(公告)日：2017-11-01
申请号：EP15873942.5
申请日：2015-11-20
申请人： Intel Corporation
发明人： OULD-AHMED-VALL, Elmoustapha , ESPASA, Roger , GUILLEN, David F. , SANCHEZ, F. Jesus , SOLE, Guillem
CPC分类号： G06F9/30029 , G06F9/30018 , G06F9/30036
摘要： An apparatus and method are described for performing a vector broadcast and XORAND logical instruction. For example, one embodiment of a processor comprises: fetch logic to fetch an instruction from memory indicating a destination packed data operand, a first source packed data operand, a second source packed data operand, and an immediate operand, and execution logic to determine a bit in the second source packed data operand based a position corresponding to the immediate value, perform a bitwise AND between the first source packed data operand and the determined bit to generate an intermediate result, perform a bitwise XOR between the destination packed data operand and the intermediate result to generate a final result, and store the final result in a storage location indicated by the destination packed data operand.
摘要翻译： 描述了用于执行矢量广播和XORAND逻辑指令的设备和方法。 例如，处理器的一个实施例包括：提取逻辑，用于从存储器提取指示目的地打包数据操作数，第一源打包数据操作数，第二源打包数据操作数和立即操作数的指令;以及执行逻辑， 基于与立即值相对应的位置在第二源打包数据操作数中执行按位与运算，在第一源打包数据运算数与所确定的位之间执行按位与运算以生成中间结果，在目的打包数据操作数和 中间结果以产生最终结果，并将最终结果存储在由目的地打包数据操作数指示的存储位置中。
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