公开(公告)号：EP2798520A1

公开(公告)日：2014-11-05

申请号：EP11878906.4

申请日：2011-12-29

申请人： Intel Corporation

发明人： MAGKLIS, Grigorios ,  CODINA, Josep M. ,  ZILLES, Craig B. ,  NEILLY, Michael ,  SAMUDRALA, Sridhar ,  MARTINEZ VICENTE, Alejandro ,  XEKALAKIS, Polychronis ,  SANCHEZ, F. Jesus ,  LUPON, Marc ,  TOURNAVITIS, Georgios ,  GIBERT CODINA, Enric ,  GOMEZ REQUENA, Crispin ,  GONZALEZ, Antonio ,  HYUSEINOVA, Mirem ,  KOTSELIDIS, Christos E. ,  LATORRE, Fernando ,  LOPEZ, Pedro ,  MADRILES, Carlos ,  MARCUELLO, Pedro ,  MARTINEZ, Raul ,  ORTEGA, Daniel ,  PAVLOU, Demos ,  STAVROU, Kyriakos A.

IPC分类号： G06F15/76 ,  G06F9/30 ,  G06F9/44

CPC分类号： G06F9/3001 ,  G06F9/30032 ,  G06F9/30087 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3842

摘要： Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction.

公开(公告)号：EP2798470A1

公开(公告)日：2014-11-05

申请号：EP11878987.4

申请日：2011-12-29

申请人： Intel Corporation

发明人： STAVROU, Kyriakos A. ,  GIBERT CODINA, Enric ,  CODINA, Josep M. ,  GOMEZ REQUENA, Crispin ,  GONZALEZ, Antonio ,  HYUSEINOVA, Mirem ,  KOTSELIDIS, Christos E. ,  LATORRE, Fernando ,  LOPEZ, Pedro ,  LUPON, Marc ,  MADRILES, Carlos ,  MAGKLIS, Grigorios ,  MARCUELLO, Pedro ,  MARTINEZ VICENTE, Alejandro ,  MARTINEZ, Raul ,  ORTEGA, Daniel ,  PAVLOU, Demos ,  TOURNAVITIS, Georgios ,  XEKALAKIS, Polychronis

IPC分类号： G06F9/06 ,  G06F9/30

CPC分类号： G06F9/3804 ,  G06F9/30047 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3848 ,  G06F12/0862 ,  G06F2212/452

摘要： Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.