公开(公告)号：EP2619654B1

公开(公告)日：2018-08-01

申请号：EP11827728.4

申请日：2011-09-26

申请人： Intel Corporation

发明人： BRETERNITZ JR, Mauricio ,  WU, Youfeng ,  WANG, Cheng ,  BORIN, Edson ,  HU, Shiliang ,  ZILLES, Craig B.

IPC分类号： G06F8/52 ,  G06F8/41 ,  G06F9/46 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

摘要： An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：EP2798520A1

公开(公告)日：2014-11-05

申请号：EP11878906.4

申请日：2011-12-29

申请人： Intel Corporation

发明人： MAGKLIS, Grigorios ,  CODINA, Josep M. ,  ZILLES, Craig B. ,  NEILLY, Michael ,  SAMUDRALA, Sridhar ,  MARTINEZ VICENTE, Alejandro ,  XEKALAKIS, Polychronis ,  SANCHEZ, F. Jesus ,  LUPON, Marc ,  TOURNAVITIS, Georgios ,  GIBERT CODINA, Enric ,  GOMEZ REQUENA, Crispin ,  GONZALEZ, Antonio ,  HYUSEINOVA, Mirem ,  KOTSELIDIS, Christos E. ,  LATORRE, Fernando ,  LOPEZ, Pedro ,  MADRILES, Carlos ,  MARCUELLO, Pedro ,  MARTINEZ, Raul ,  ORTEGA, Daniel ,  PAVLOU, Demos ,  STAVROU, Kyriakos A.

IPC分类号： G06F15/76 ,  G06F9/30 ,  G06F9/44

CPC分类号： G06F9/3001 ,  G06F9/30032 ,  G06F9/30087 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3842

摘要： Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction.

公开(公告)号：EP2619654A2

公开(公告)日：2013-07-31

申请号：EP11827728.4

申请日：2011-09-26

申请人： Intel Corporation

发明人： BRETERNITZ JR, Mauricio ,  WU, Youfeng ,  WANG, Cheng ,  BORIN, Edson ,  HU, Shiliang ,  ZILLES, Craig B.

IPC分类号： G06F9/30 ,  G06F9/305 ,  G06F9/06 ,  G06F15/76

CPC分类号： G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

摘要： An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.