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    TIME-TO-DIGITAL CONVERTERS, DIGITAL-PHASE-LOCKED LOOPS AND METHODS FOR OPERATING TIME-TO-DIGITAL CONVERTERS
    2.
    发明公开
    TIME-TO-DIGITAL CONVERTERS, DIGITAL-PHASE-LOCKED LOOPS AND METHODS FOR OPERATING TIME-TO-DIGITAL CONVERTERS 审中-公开

    公开(公告)号：EP4343454A1

    公开(公告)日：2024-03-27

    申请号：EP22197069.2

    申请日：2022-09-22

    申请人： INTEL Corporation

    发明人： DEGANI, Ofir ,  SHUMAKER, Evgeny

    IPC分类号： G04F10/00 ,  H03L7/08 ,  H03L7/087

    摘要： A time-to-digital converter may include a delay circuit configured to delay a first signal to generate a plurality of delayed first signals; a circuit configured to generate a first analog oscillating signal and a second analog oscillating signal using an input second signal, wherein the second analog oscillating signal is phase offset with respect to the first analog oscillating signal; a first plurality of sample circuits, each configured to sample the first analog oscillating signal in accordance with an associated delayed first signal of the delayed first signals, and a second plurality of sample circuits, each configured to sample the second analog oscillating signal in accordance with an associated delayed first signal of the delayed first signals. Each of the delayed first signals is provided to a respective sample circuit of the first plurality of sample circuits and to a respective sample circuit of the second plurality of sample circuits.

    HIGH-RESOLUTION AND AGILE FREQUENCY MEASUREMENT
    3.
    发明公开
    HIGH-RESOLUTION AND AGILE FREQUENCY MEASUREMENT 审中-公开

    公开(公告)号：EP3975430A1

    公开(公告)日：2022-03-30

    申请号：EP21193062.3

    申请日：2021-08-25

    申请人： INTEL Corporation

    发明人： SHUMAKER, Evgeny ,  DEGANI, Ofir ,  LEVINGER, Run ,  BERSHANSKY, Sergey

    IPC分类号： H03L7/085 ,  H03L7/087 ,  H03L7/093 ,  H03L7/099

    摘要： An apparatus for generating a frequency estimate of an output signal includes a reference signal generator configured to generate a reference clock signal. The apparatus includes frequency estimation circuitry configured to generate a cycle count based frequency estimation of the output signal based on the reference clock signal and a clock cycle count of the output signal. The frequency estimation circuitry further generates a fractional frequency estimation of the output signal based on the reference clock signal and a plurality of time-to-digital conversion phase samples of the output signal. The frequency estimation circuitry further generates the frequency estimate of the output signal using the cycle count based frequency estimation within a range and a frequency error determined from the fractional frequency estimation. The plurality of time-to-digital conversion phase samples and the cycle count based frequency estimation use a same number of reference clock cycles of the reference clock signal.

    METHODS AND DEVICES FOR ASYMMETRIC FREQUENCY SPREADING
    5.
    发明公开
    METHODS AND DEVICES FOR ASYMMETRIC FREQUENCY SPREADING 审中-公开

    公开(公告)号：EP4020820A1

    公开(公告)日：2022-06-29

    申请号：EP20216333.3

    申请日：2020-12-22

    申请人： INTEL Corporation

    发明人： DEGANI, Ofir ,  BANIN, Rotem ,  BANIN, Elan ,  SHUMAKER, Evgeny ,  GROSS, Shahar

    IPC分类号： H04B1/04

    摘要： A wireless communication device for asymmetrical frequency spreading including a processor configured to receive a frequency band message comprising a maximum difference and a minimum difference, wherein the maximum difference is between a maximum frequency of a sub-band and a signal frequency, and wherein the minimum difference is between the minimum frequency of the sub-band and the signal frequency compare the maximum difference and the minimum difference with each other; and generate a frequency shift based on the comparison.