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    QUADRATURE PHASE DETECTOR CIRCUIT, QUADRATURE PHASE CORRECTOR, MULTI-ANTENNA RADIO CIRCUIT, RADIO STATION AND METHOD
    4.
    发明公开
    QUADRATURE PHASE DETECTOR CIRCUIT, QUADRATURE PHASE CORRECTOR, MULTI-ANTENNA RADIO CIRCUIT, RADIO STATION AND METHOD 审中-公开
    正交相位检测器电路，正交相位校正器，多天线无线电电路，无线电台和方法

    公开(公告)号：EP3311492A1

    公开(公告)日：2018-04-25

    申请号：EP15730128.4

    申请日：2015-06-16

    申请人： Telefonaktiebolaget LM Ericsson (PUBL)

    发明人： EK, Staffan ,  MATTISSON, Sven ,  PÅHLSSON, Tony ,  SJÖLAND, Henrik

    IPC分类号： H03L7/085 ,  H03L7/18 ,  H03L7/22

    CPC分类号： H03L7/085 ,  H03L7/18 ,  H03L7/22 ,  H04B1/04 ,  H04B7/08 ,  H04B2001/0491

    摘要： A quadrature phase detector circuit for a multi-antenna radio circuit comprising a plurality of frequency synthesizers using a common reference oscillator signal is disclosed. The quadrature phase detector comprises a first circuit arranged to collect a first state value indicating an inner state of a first quadrature signals generating frequency divider circuit of a first frequency synthesizer of the plurality of frequency synthesizers and a second state value indicating an inner state of a second quadrature signals generating frequency divider circuit of a second frequency synthesizer of the plurality of frequency synthesizers, a second circuit arranged to determine from the first state value and the second state value whether quadrature signals of the first frequency synthesizer and quadrature signals of the second frequency synthesizer are in-phase or out-of-phase, and a third circuit arranged to provide an output signal indicating whether the quadrature signals of the first frequency synthesizer and the quadrature signals of the second frequency synthesizer are in-phase or out-of-phase.

    SIMULTANEOUS OSCILLATION AND FREQUENCY TRACKING OF MULTIPLE RESONANCES VIA DIGITALLY IMPLEMENTED PHASE-LOCKED LOOP ARRAY
    5.
    发明公开
    SIMULTANEOUS OSCILLATION AND FREQUENCY TRACKING OF MULTIPLE RESONANCES VIA DIGITALLY IMPLEMENTED PHASE-LOCKED LOOP ARRAY 审中-公开
    通过数字执行锁相环阵列实现多谐振动的同时振荡和频率跟踪

    公开(公告)号：EP3213414A1

    公开(公告)日：2017-09-06

    申请号：EP15791452.4

    申请日：2015-10-27

    申请人： Massachusetts Institute of Technology

    发明人： CERMAK, Nathan ,  OLCUM, Selim ,  WASSERMAN, Steven, Charles ,  MANALIS, Scott, R.

    IPC分类号： H03L7/00 ,  G01N11/16 ,  H03L7/22

    摘要： Systems and Methods for controlling one or more mechanical resonators and determining information from resonant shift of the reonator(s) behavior, including at least one mechanical resonator, an excitation element for driving the resonator(s), a sensor for monitoring the motion of the resonator(s), at least one phase locked loop (PLL) in feedback between the excitation and monitoring elements, wherein each PLL is configured to operate at or near a different resonant mode of the resonator(s), and a processor for determining information from PLL internal signals indicative of a resonator frequency shift.

    摘要翻译： 用于控制一个或多个机械谐振器并根据一个或多个谐振器行为的谐振移位确定信息的系统和方法，包括至少一个机械谐振器，用于驱动谐振器的激励元件，用于监测 谐振器，在激励和监测元件之间的反馈中的至少一个锁相环（PLL），其中每个PLL被配置为在谐振器的不同谐振模式处或附近工作，以及处理器，用于确定信息 来自指示谐振器频移的PLL内部信号。

    Clock generation circuit
    7.
    发明公开
    Clock generation circuit 审中-公开
    Takterzeugungsschaltung

    公开(公告)号：EP2546991A1

    公开(公告)日：2013-01-16

    申请号：EP11305929.9

    申请日：2011-07-15

    申请人： Thomson Licensing

    发明人： Kropp, Holger ,  Abeling, Stefan ,  Schuetze, Herbert

    IPC分类号： H03L7/081 ,  H03L7/22

    CPC分类号： H03L7/22 ,  H03L7/0814

    摘要： A clock generation circuit comprises an internal clock signal source providing an internal clock signal (CLK_INT) and a synchronization device for synchronization the internal clock signal (CLK_INT) with a reference clock signal (CLK_REF) provided externally from the clock generation circuit. The synchronization device comprises n delay locked loop circuits (Sync_DLL_0, Sync_DLL_1, Sync_DLL_2, Sync_DLL_3), n being an integer greater than 1, each delay locked loop circuit (Sync_DLL_0, Sync_DLL_1, Sync_DLL_2, Sync_DLL_3) having a clock input for receiving the internal clock signal (CLK_INT) and a clock output for providing an output clock signal (CLK(0), CLK(1), CLK(2), CLK(3)) with an individual phase shift that is adjustable. The synchronization device further comprises a multiplexer (CLKMUX) having n inputs and an output wherein each of the n inputs is connected to an output of one of the n delay locked loops (Sync_DLL_0, Sync_DLL_1, Sync_DLL_2, Sync_DLL_3) and a control circuit. The control circuit is adapted to adjust at least one of the delay locked loop circuits (Sync_DLL_0, Sync_DLL_1, Sync_DLL_2, Sync_DLL_3) for providing an individual phase shift according to a current phase shift and to select that input of the multiplexer (CLKMUX) that receives an output clock signal (CLK(0), CLK(1), CLK(2), CLK(3)) of the adjusted delay locked loop circuit (Sync_DLL_0, Sync_DLL_1, Sync_DLL_2, Sync_DLL_3) that is synchronized in frequency and phase with the reference clock signal (CLK_REF), wherein the output of the multiplexer (CLKMUX) provides that output clock signal as synchronized clock signal (CLK_SYNC), and wherein
    the control circuit is adapted to toggle between the n delay locked loop circuits (Sync_DLL_0, Sync_DLL_1, Sync_DLL_2, Sync_DLL_3), in a way that the phase of the internal clock signal (CLK_INT) is successively shifted according to the current phase shift between the internal clock signal (CLK_INT) and the reference clock signal (CLK_REF).

    摘要翻译： 时钟发生电路包括提供内部时钟信号（CLK_INT）的内部时钟信号源和用于使内部时钟信号（CLK_INT）与从时钟发生电路外部提供的参考时钟信号（CLK_REF）同步的同步装置。 同步装置包括n个延迟锁定环电路（Sync_DLL_0，Sync_DLL_1，Sync_DLL_2，Sync_DLL_3），n是大于1的整数，每个具有用于接收内部时钟的时钟输入的延迟锁定环电路（Sync_DLL_0，Sync_DLL_1，Sync_DLL_2，Sync_DLL_3） 信号（CLK_INT）和用于提供可调整的单个相移的输出时钟信号（CLK（0），CLK（1），CLK（2），CLK（3））的时钟输出。 同步装置还包括具有n个输入和输出的多路复用器（CLKMUX），其中n个输入中的每一个连接到n个延迟锁定环（Sync_DLL_0，Sync_DLL_1，Sync_DLL_2，Sync_DLL_3）中的一个的输出和控制电路。 控制电路适于调整延迟锁定环路电路（Sync_DLL_0，Sync_DLL_1，Sync_DLL_2，Sync_DLL_3）中的至少一个，用于根据当前相移提供单个相移，并选择接收到的多路复用器（CLKMUX）的输入 与频率和相位同步的经调整的延迟锁定环电路（Sync_DLL_0，Sync_DLL_1，Sync_DLL_2，Sync_DLL_3）的输出时钟信号（CLK（0），CLK（1），CLK（2），CLK（3） 参考时钟信号（CLK_REF），其中所述多路复用器（CLKMUX）的输出将所述输出时钟信号提供为同步时钟信号（CLK_SYNC），并且其中所述控制电路适于在所述n个延迟锁定环路电路（Sync_DLL_0，Sync_DLL_1， Sync_DLL_2，Sync_DLL_3），使得内部时钟信号（CLK_INT）的相位根据内部时钟信号（CLK_INT）和参考时钟信号（CLK_REF）之间的当前相移被连续移位。