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7 条记录 (耗时 0.011 秒)

    DETECTION OF ADJACENT TWO BIT ERRORS IN A CODEWORD
    2.
    发明公开
    DETECTION OF ADJACENT TWO BIT ERRORS IN A CODEWORD 审中-公开

    公开(公告)号：EP3716490A1

    公开(公告)日：2020-09-30

    申请号：EP20157895.2

    申请日：2020-02-18

    申请人： INTEL Corporation

    发明人： WU, Wei ,  KOZHIKKOTTU, Vivek ,  SOMASEKHAR, Dinesh ,  STEPHAN, Jon ,  KWON, Kon-Woo

    IPC分类号： H03M13/19 ,  H03M13/17 ,  G06F11/10

    摘要： In an embodiment, a processor includes error correction code (ECC) circuitry to: receive a codeword comprising data bits and parity bits; generate, using a parity checking matrix H, a syndrome vector associated with the received codeword, where the parity-checking matrix H comprises a data segment comprising N data columns and a parity segment comprising K parity columns, where a total quantity of data columns in the data segment with even weight is equal to N+K-2 (K-1) +1; and detect an adjacent two bit error in the codeword based on a comparison of the syndrome vector to the parity checking matrix H. Other embodiments are described and claimed.

    TEMPERATURE DEPENDENT MULTIPLE MODE ERROR CORRECTION
    4.
    发明公开
    TEMPERATURE DEPENDENT MULTIPLE MODE ERROR CORRECTION 审中-公开

    公开(公告)号：EP3368984A1

    公开(公告)日：2018-09-05

    申请号：EP16860481.7

    申请日：2016-09-30

    申请人： INTEL Corporation

    发明人： WU, Wei ,  AUGUSTINE, Charles ,  TOMISHIMA, Shigeki ,  LU, Shih-Lien L. ,  TSCHANZ, James W.

    IPC分类号： G06F11/10

    CPC分类号： H03M13/05 ,  G06F11/1048 ,  H03M13/1515 ,  H03M13/353 ,  H03M13/611

    摘要： In one embodiment, temperature dependent, multiple mode error correction in accordance with one aspect of this disclosure, is employed for a memory circuit containing arrays of memory cells. In one embodiment, a temperature sensor coupled to an array is configured to provide an output signal which is a function of the temperature of the array of memory cells. Multiple mode error correction code (ECC) logic having an input coupled to an output of the temperature sensor, is configured to encode write data and decode read data for the array of memory cells in an error correction code in one of a plurality of error correction modes as a function of the temperature of the array of memory cells. Other aspects are described herein.

    PHYSICALLY UNCLONABLE FUNCTION REDUNDANT BITS
    5.
    发明公开
    PHYSICALLY UNCLONABLE FUNCTION REDUNDANT BITS 审中-公开
    REDUNDANTE BITS MIT PHYSIKALISCH UNKLONBAREN FUNKTIONEN

    公开(公告)号：EP3059863A1

    公开(公告)日：2016-08-24

    申请号：EP16153476.3

    申请日：2014-11-19

    申请人： Intel Corporation

    发明人： KOEBERL, Patrick ,  WU, Wei ,  LI, Jiangtao

    IPC分类号： H03K19/003 ,  H04L9/32 ,  H04L9/08

    CPC分类号： H04L9/3278 ,  G09C1/00 ,  H03K19/003 ,  H04L9/0866

    摘要： Embodiments of an invention for using physically unclonable function redundant bits are disclosed. In one embodiment, an integrated circuit includes a PUF cell array and redundancy logic. The PUF cell array includes a plurality of redundant cells and is to provide a raw PUF value. The redundancy logic is to generate a redirection list to be used to replace each of one or more bits of the raw PUF value with a redundant bit value from one of the redundant cells.

    摘要翻译： 公开了使用物理上不可克隆的功能冗余位的发明的实施例。 在一个实施例中，集成电路包括PUF单元阵列和冗余逻辑。 PUF单元阵列包括多个冗余单元，并且提供原始PUF值。 冗余逻辑是生成重定向列表，以用来从冗余单元之一中的冗余比特值替换原始PUF值的一个或多个比特中的每一个。