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    DIGITALLY CONTROLLED TWO-POINTS EDGE INTERPOLATOR
    3.
    发明公开
    DIGITALLY CONTROLLED TWO-POINTS EDGE INTERPOLATOR 审中-公开
    数字控制的两点边界插值器

    公开(公告)号：EP3160048A1

    公开(公告)日：2017-04-26

    申请号：EP16186694.2

    申请日：2016-08-31

    申请人： Intel IP Corporation

    发明人： DEGANI, Ofir ,  BANIN, Rotem ,  SIEVERT, Sebastian

    IPC分类号： H03M1/82 ,  H03M1/68 ,  H03F3/24 ,  H03F3/217

    CPC分类号： H04L7/002 ,  H03F3/2178 ,  H03F3/245 ,  H03M1/68 ,  H03M1/82 ,  H04L7/0091 ,  H04L27/365

    摘要： Described herein are technologies related to an implementation of a digital-to-time converter (DTC) circuitry that utilizes a first interpolation and a second and finer interpolation to increase interpolation ranges. The DTC circuitry generates a fine-phase modulated signal generating at least two correlated signals, and generating coarse and fine interpolations of the correlated signals.

    摘要翻译： 这里描述的是与数字到时间转换器（DTC）电路的实现有关的技术，该电路利用第一内插和第二和更精细的内插来增加内插范围。 DTC电路生成精相调制信号，该精相调制信号生成至少两个相关信号，并且生成相关信号的粗略和精细内插。

    LOW DROP OUT COMPENSATION TECHNIQUE FOR REDUCED DYNAMIC ERRORS IN DIGITAL-TO-TIME CONVERTERS
    4.
    发明公开
    LOW DROP OUT COMPENSATION TECHNIQUE FOR REDUCED DYNAMIC ERRORS IN DIGITAL-TO-TIME CONVERTERS 审中-公开
    数字时间转换器中降低动态误差的低压差补偿技术

    公开(公告)号：EP3264706A3

    公开(公告)日：2018-04-18

    申请号：EP17177264.3

    申请日：2017-06-21

    申请人： Intel IP Corporation

    发明人： SIEVERT, Sebastian ,  DEGANI, Ofir ,  GORDON, Eshel

    IPC分类号： H04L27/36 ,  G05F1/613 ,  H04B1/40

    CPC分类号： H04B1/40 ,  G05F1/613 ,  G05F3/205 ,  G05F3/26 ,  H03C3/00 ,  H04B1/04 ,  H04L27/361

    摘要： An apparatus comprises a radio frequency (RF) transceiver circuit; a phase modulator that comprises digital-to-time converter (DTC) circuitry configured to convert a digital value to a specified signal phase of a signal transmitted by the RF transceiver circuit; low drop out regulator (LDO) circuitry operatively coupled to the DTC circuitry, wherein a bias current of the LDO circuitry is adjustable; and logic circuitry operatively coupled to the LDO circuitry and DTC circuitry, wherein the logic circuitry is configured to set the adjustable bias current of the LDO circuitry according to a digital value input to the DTC circuitry.

    摘要翻译： 一种装置包括射频（RF）收发器电路; 包括数字 - 时间转换器（DTC）电路的相位调制器，所述数字 - 时间转换器电路被配置为将数字值转换为由所述RF收发器电路发送的信号的指定信号相位; 可操作地耦合到DTC电路的低压降调节器（LDO）电路，其中LDO电路的偏置电流是可调节的; 以及可操作地耦合到LDO电路和DTC电路的逻辑电路，其中逻辑电路被配置为根据输入到DTC电路的数字值来设置LDO电路的可调偏置电流。

    AN APPARATUS AND A METHOD FOR GENERATING A RADIO FREQUENCY SIGNAL
    7.
    发明公开
    AN APPARATUS AND A METHOD FOR GENERATING A RADIO FREQUENCY SIGNAL 审中-公开

    公开(公告)号：EP3353974A1

    公开(公告)日：2018-08-01

    申请号：EP15779018.9

    申请日：2015-09-25

    申请人： Intel IP Corporation

    发明人： SIEVERT, Sebastian ,  DEGANI, Ofir ,  RAVI, Ashoke ,  BANIN, Rotem

    IPC分类号： H04L27/36

    CPC分类号： H04L27/362 ,  H03C3/40 ,  H03C2200/0058 ,  H03M1/66

    摘要： An apparatus for generating a radio frequency signal based on a symbol within a constellation diagram is provided. The constellation diagram is spanned by a first axis representing an in-phase component and an orthogonal second axis representing a quadrature component. The apparatus includes a processing unit configured to select a segment of a plurality of segments of the constellation diagram containing the symbol. The segment is delimited by a third axis and a fourth axis each crossing the origin of the constellation diagram and spanning an opening angle of the segment of less than about 90°. The processing unit is further configured to calculate a first coordinate of the symbol with respect to the third axis, and a second coordinate of the symbol with respect to the fourth axis. The apparatus further includes a plurality of digital-to-analog converter cells configured to generate the radio frequency signal using the first coordinate and the second coordinate.