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公开(公告)号：EP4447323A1
公开(公告)日：2024-10-16
申请号：EP24169129.4
申请日：2024-04-09
摘要： A transmitter includes a first circuit to generate multiphase pulses, and a second circuit to mix a set of in-phase (I) data and quadrature (Q) data with the multiphase pulses and to generate an output radiofrequency (RF) signal. The multiple pulses include multiple I pulses and multiple Q pulses each comprising a pulse that includes a duty cycle such that a first null appears at a third harmonic frequency in a frequency spectrum of the pulse.
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公开(公告)号：EP4338286A1
公开(公告)日：2024-03-20
申请号：EP22725599.9
申请日：2022-05-02
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公开(公告)号：EP4256708A2
公开(公告)日：2023-10-11
申请号：EP21827463.7
申请日：2021-11-18
发明人： WU, Zhengzheng , SONG, Chao , NAGARAJAN, Karthik
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公开(公告)号：EP4199365A1
公开(公告)日：2023-06-21
申请号：EP22213204.5
申请日：2022-12-13
申请人： INTEL Corporation
发明人： BEN-BASSAT, Assaf , DEGANI, Ofir , BANIN, Elan , GROSS, Shahar , SKLIAR, Phillip
摘要： A method for compensating signal nonlinearities includes generating a local oscillator (LO) signal and performing phase modulation of the LO signal to generate a phase-modulated LO signal. The phase modulation is based on applying at least one digital-to-time converter (DTC) code of a plurality of DTC codes to a rising edge signal portion and a falling edge signal portion associated with the LO signal. Nonlinearities associated with the rising edge signal portion and the falling edge signal portion are determined. The at least one DTC code is adjusted based on the nonlinearities.
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公开(公告)号：EP3965301A1
公开(公告)日：2022-03-09
申请号：EP21193981.4
申请日：2021-08-31
申请人： NXP B.V.
摘要： Various embodiments relate to a single slope analog to digital converter (ADC), including: a voltage slope generator; a reference voltage generator configured to generate a first reference voltage, a second reference voltage, and a third reference voltage, where the first reference voltage equals the sum of the second reference voltage and the third reference voltage; a first comparator configured to compare a voltage to a voltage output from the voltage slope generator; a first register configured to store a first count based upon the first reference voltage being input into the first comparator; a second register configured to store a second count based upon the second reference voltage being input into the first comparator; a third register configured to store a third count based upon the third reference voltage being input into the first comparator; a fourth register configured to store a fourth count based upon a first input voltage being input into the first comparator, wherein the first input voltage is the voltage to be converted to a digital value by the ADC; and an output circuit configured to calculate a digital value for the first input voltage based upon the first, second, third, and fourth counts.
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公开(公告)号：EP3353976B1
公开(公告)日：2020-10-21
申请号：EP15779021.3
申请日：2015-09-25
申请人： Intel IP Corporation
发明人： MENKHOFF, Andreas
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公开(公告)号：EP3353886A1
公开(公告)日：2018-08-01
申请号：EP16774567.8
申请日：2016-09-12
申请人： Osram Sylvania Inc.
发明人： XIAO, Peng , ZIEGLER, Markus
IPC分类号： H02M7/5395 , H03M1/68 , H03M1/82 , H05B33/08
CPC分类号： H02M3/157 , H02M3/156 , H02M7/5395 , H02M2001/0012 , H03M1/68 , H03M1/822 , H05B33/08
摘要： A digitally compensated hysteretic power supply with enhanced resolution is provided. Such a power supply includes a comparator that is used to compare a load current sense signal with an internal signal generated from a digital-to-analog converter (DAC). A compensation circuit at a DAC input operates to improve current accuracy beyond the given DAC resolution. The current sense signal is converted to its digital equivalent, which is fed to a proportional-integral (PI) compensation loop, which in turn generates a relatively precise high resolution DAC input value. The DAC uses the higher part of the DAC value. The lower part of the DAC value is treated as a duty cycle number, and the DAC output is toggled between two levels at this duty cycle. This toggling generates a current output signal having a value that is the average of the two toggled values.
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公开(公告)号：EP3340470A1
公开(公告)日：2018-06-27
申请号：EP16205845.7
申请日：2016-12-21
申请人： Intel IP Corporation
CPC分类号： H03M1/82 , H03K5/131 , H03K5/135 , H03K2005/00052 , H03K2005/00058 , H03M1/007 , H04W88/02
摘要： An apparatus for interpolating between a first signal edge and a second signal edge is provided. The apparatus includes a plurality of interpolation cells coupled to a common node. At least one of the plurality of interpolation cells is configured to supply, based on a control word, the first signal edge and/or the second signal edge to the common node. Further, the apparatus includes a control circuit configured to activate all of the plurality interpolation cells in a first mode of operation, and to deactivate part of the plurality of interpolation cells in a second mode of operation.
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公开(公告)号：EP2996295B1
公开(公告)日：2017-06-14
申请号：EP15184945.2
申请日：2015-09-11
申请人： Xiaomi Inc.
发明人： DING, Yi , LIU, Xin , GAO, Ziguang
CPC分类号： H04L25/4902 , H03K7/08 , H04B10/1141
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公开(公告)号：EP2159918A3
公开(公告)日：2012-04-25
申请号：EP09010822.6
申请日：2009-08-24
申请人： Yamaha Corporation
CPC分类号： H03F3/2173 , H03M1/0639 , H03M1/0673 , H03M1/822 , H03M3/328 , H03M3/50 , H03M3/506 , H03M7/3026
摘要： The present invention provides a D/A converter circuit which enables D/A conversion with a high precision and can prevent occurrence of a limit cycle component in the case where an input signal is low, and can also prevent the effect of dither signal from occurring in an analog signal which is a D/A conversion result.
A dither signal generation section 505 outputs a dither signal (DITHER) which is an alternating current signal and a reversal dither signal (DITHER_N) inverted from the dither signal. A DEM decoder 502 processes an input digital signal including a component of the dither signal (DITHER), and outputs a plurality of lines of time-series digital signals having a density of "1" or "0" conforming to the input digital signal to be processed. An analog addition section 503 converts a plurality of lines of time-series digital signals and the reversal dither signal (DITHER_N) into an analog signal respectively and adds them, and outputs an analog signal which is a D/A conversion result.
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