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公开(公告)号：EP3360247A1
公开(公告)日：2018-08-15
申请号：EP16853208.3
申请日：2016-10-06
发明人： STERNKLAR, Shmuel , BEN-AYUN, Moshe
CPC分类号： H04L27/361 , G01R25/04 , H03C3/40
摘要： A method of amplifying a phase shift, comprises: receiving an input signal in response to an output signal; generating a reference signal; varying a modulation of at least one of the signals such that a ratio between modulation amplitudes of the input and reference signals is at least 0.9 and at most 1.1, and a phase difference between the reference and the input signals is from about 0.9 pi to about 1.1 pi; forming an output signal which comprises a sum of the reference and input signals, following the variation; and filtering the output signal by a bandpass filter to form a filtered output signal, wherein a bandwidth of the bandpass filter is selected such that XG
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2.发明公开FAST HOPPING FREQUENCY SYNTHESIZER USING AN ALL DIGITAL PHASED LOCKED LOOP (ADPLL) 审中-公开SYNTHESIZER MIT SCHNELLENFREQUENZSPRÜNGENUNDVOLLSTÄNDIGDIGITALEM PHASENREGELKREIS
公开(公告)号：EP1882304A4
公开(公告)日：2017-04-26
申请号：EP06770176
申请日：2006-05-10
发明人： TAL NIR , STASZOWSKI ROBERT B , FRIEDMAN OFER
CPC分类号： H04B1/7136 , H03C3/40 , H03D3/007 , H03L7/08 , H03L7/0991 , H04B1/71635 , H04B1/71637 , H04B2001/71365
摘要： A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/f T of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency. A mixer applies the waveform to the I and Q data samples prior to conversion to the digital domain.
摘要翻译： 一种新颖且有用的快速跳频频率合成器和与之相关的发射机。 频率合成器和发射器包含一个适用于开环操作的数字控制振荡器（DCO）。 通过改变振荡器调谐字（OTW）来模拟UWB发射机的三个振荡器来实现瞬时频率切换。 在一个实施例中，DCO可以在用于构建DCO的变容二极管器件的1 / fT内瞬时改变频率。 在数据包发送或接收开始之前，全数字锁相环（ADPLL）用于离线校准。 开关期间的任何相移由发射机中的数字电路跟踪。 在第二实施例中，通过使用数字控制振荡器（NCO）来提供附加的频率精确度，该数字控制振荡器的功能是产生有效地改变合成频率的精细分辨率复指数波形。 在转换到数字域之前，混频器将波形应用于I和Q数据采样。
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公开(公告)号：EP2709274A4
公开(公告)日：2014-11-19
申请号：EP12786390
申请日：2012-02-06
发明人： ONISHI MASAHIKO
CPC分类号： H04L25/10 , H03C3/40 , H03F1/3247 , H03F1/3294 , H03F1/34 , H03F3/24 , H03F3/245 , H04B2001/0433 , H04L27/361 , H04L27/364 , H04L27/368
摘要： A quadrature modulation error is compensated without providing an additional feedback loop for detecting the quadrature modulation error. An amplifier circuit includes: a quadrature modulator 33; an amplifier 2 that amplifies a quadrature-modulated signal; a distortion compensation section 4 that compensates distortion to be caused in the amplifier based on first compensation coefficients; a quadrature modulation error compensation section 9 that compensates for a quadrature modulation error; an updating section 10b that updates second compensation coefficients for compensating the quadrature modulation error; an error estimation section 10a that estimates an error of the quadrature modulation error; and a prediction section that calculates a prediction value of an output of the amplifier after updating of the second compensation coefficients. The second compensation coefficients are updated based on the estimated error. The prediction value is calculated based on the estimated error and the amplifier output. The distortion compensation section 4 calculates the first compensation coefficient, based on the prediction value.
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公开(公告)号：EP1368891B1
公开(公告)日：2013-12-25
申请号：EP01989865.9
申请日：2001-10-24
发明人： BENGTSSON, Erik, L. , HADJICHRISTOS, Aristotle , JUSTICE, Scott, R. , CAMP, William, O., Jr. , GORE, Charles, Jr. , PEHLKE, David, R. , CAIRNS, Steven, G. , KHATIBZADEH, M., Ali , SCHLANG, Jeffrey
CPC分类号： H03F3/24 , H03C3/0941 , H03C3/0966 , H03C3/0975 , H03C3/0983 , H03C3/40 , H03F2200/336 , H03F2200/504 , H04L27/362
摘要： A digital signal processor generates in-phase, quadrature-phase and amplitude signals from a baseband signal. A modulator modulates the in-phase and quadrature-phase signals to produce a modulated signal. A phase locked loop is responsive to the modulated signal. The phase locked loop includes a controlled oscillator having a controlled oscillator input. An amplifier includes a signal input, amplitude control input and an output. The signal input is responsive to the controlled oscillator output and the amplitude control input is responsive to the amplitude signal. The phase locked loop that is responsive to the modulated signal includes a controlled oscillator output and a feedback loop between the controlled oscillator input and the controlled oscillator output. The feedback loop includes a mixer that is responsive to a local oscillator. The modulator may be placed in the phase locked loop. In particular, the modulator may be placed in the feedback loop between the controlled oscillator output and the mixer, between the local oscillator and the mixer, or between the mixer and the controlled oscillator input.
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公开(公告)号：EP1450479B1
公开(公告)日：2012-03-28
申请号：EP03003830.1
申请日：2003-02-20
CPC分类号： H03C3/40 , H03F1/0227 , H03F1/0277 , H03F1/32 , H03F3/211 , H03F2200/294 , H03F2200/372 , H03G3/3047 , H04L27/361
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公开(公告)号：EP2176948B1
公开(公告)日：2011-09-28
申请号：EP08773379.6
申请日：2008-06-10
发明人： RICHT, Norbert , LORENZ, Petr
CPC分类号： H03C3/40 , H04L27/12 , H04L27/32 , H04L27/362
摘要： In order to produce a broadband-frequency-modulated output signal s (S3), the carrier frequency (fc) of which can be adjusted in a wide frequency range, a frequency-modulated signal (S1) is produced at any desired fixed carrier frequency (fo), is then converted to IQ signals (Si2,Sq2), and the IQ signals produced in this way are then combined with the desired carrier frequency (fc) by IQ modulation to form the frequency-modulated output signal. IQ signals that are produced are preferably low-pass-filtered before IQ modulation.
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7.发明公开IQ modulation systems and methods that use separate phase and amplitude signal paths 审中-公开I / Q调制器可以获得更多的信号
公开(公告)号：EP2330733A1
公开(公告)日：2011-06-08
申请号：EP10180932.5
申请日：2001-10-24
发明人： Bengtsson, Erik L. , Hadjichristos, Aristotele , Justice, Scott R. , Camp, William, O., Jr. , Gore, Charles, Jr. , Pehlke, David R. , Cairns, Steven G. , Khatibzadeh, Ali M. , Schlang, Jeffrey
CPC分类号： H03F3/24 , H03C3/0941 , H03C3/0966 , H03C3/0983 , H03C3/40 , H03F2200/336 , H03F2200/504 , H04L27/362
摘要： A modulation system comprising: a digital signal processor that generates in-phase, quadrature-phase and amplitude signals from a baseband signal; a modulator that modulates the in-phase and quadrature-phase signals to produce a modulated signal; a phase locked loop that is responsive to the modulated signal, the phase locked loop including a controlled oscillator having a controlled oscillator output; and an amplifier having a signal input, an amplitude control input and an output, wherein the signal input is responsive to the controlled oscillator output and the amplitude control input is responsive to the amplitude signal.
摘要翻译： 一种调制系统，包括：数字信号处理器，其从基带信号产生同相，正交相位和幅度信号; 调制器，其对同相和正交相位信号进行调制以产生调制信号; 响应于调制信号的锁相环，所述锁相环包括具有受控振荡器输出的受控振荡器; 以及具有信号输入，振幅控制输入和输出的放大器，其中所述信号输入响应所述受控振荡器输出，并且所述幅度控制输入响应于所述振幅信号。
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公开(公告)号：EP1665533B1
公开(公告)日：2008-08-20
申请号：EP03754845.0
申请日：2003-09-25
申请人： Thomson Licensing
CPC分类号： H03C3/40 , H04L27/2647
摘要： The disclosed embodiments relate to a digital radio frequency (RF) circuit (100) that creates a signal in a desired range in a frequency spectrum. The RF circuit (100) comprises circuitry (104) that produces a first sample data modulated signal (105) having a first frequency and a first sample data clock rate. An up-sampler modulator (108) receives the first sample data modulated signal and produces a second sample data modulated signal (109) having a second frequency and a second sample data clock rate. The RF circuit (100) may also comprise circuitry (112) that receives the first sample data modulated signal and the second sample data modulated signal and delivers one of the first sample data modulated signal (105) and the second sample data modulated signal (109) for further processing depending on which sample data modulated signal exhibits desirable characteristics for a given operating environment.
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公开(公告)号：EP1810413A1
公开(公告)日：2007-07-25
申请号：EP04801280.1
申请日：2004-12-01
申请人： Nokia Corporation
发明人： SHAKESHAFT, Niall , VEPSÄLÄINEN, Jussi Heikki , ELORANTA, Petri Tapani , SEPPINEN, Pauli Mikael
IPC分类号： H04B1/69
CPC分类号： H03M1/745 , H03C3/40 , H03D7/1441 , H04B1/04 , H04B2001/0491 , H04L27/36
摘要： An RF transmitter having two digital to RF-conversion devices that combine the D/A conversion function and the upconversion function by a RF-carrier or IF-signal. The device comprises a plurality of parallel unit cells, each of which is a mixer cell type converter having a differential data switch section connected in series to a differential LO-switch pair. The differential LO-switch is further connected in series to a current source. Each unit cell is adapted to receive a control voltage indicative of a data signal value.
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公开(公告)号：EP1683269A4
公开(公告)日：2007-04-04
申请号：EP04818608
申请日：2004-10-29
发明人： YANG JEFFERY MING-JER , NISHIMOTO MATT , LAN XING , BATTUNG MICHAEL , WANG ROBERT , CHUNG YUN-HO
CPC分类号： H03F3/72 , H03C3/40 , H03F1/0277 , H03F3/211 , H03F2200/372
摘要： An electronically programmable multimode circuit is described. More particularly, the present invention is an electronically programmable multimode circuit that includes a first path and a second path wherein a mode and a signal directional flow direction is controlled through the selective biasing of the first path and the second path. A multimode circuit is produced that contains modes such as a phase shifter mode, and IQ modulation mode, an amplifier mode, a mixer mode, and a multiplier mode.
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