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1.发明公开Method for storing pre-organised groups of related information files in a data processing system 失效在数据处理系统中存储相关信息文件的组织组的方法
公开(公告)号：EP0319147A3
公开(公告)日：1991-12-18
申请号：EP88310532.2
申请日：1988-11-09
发明人： Auslander, Marc Alan , Chang, Albert , Morgan, Stephen Paul , O'Quin, John Thomas , O'Quin, John Claude
CPC分类号： G06F3/0601 , G06F2003/0697
摘要： A data processing method for storing groups of related information in a storage subsystem of a data processing system in which the storage subsystem includes one or more storage devices having a plurality of block addressable storage locations (blocks or sectors) each of which stores a predetermined fixed number of bytes of said information. The method includes the step of establishing allocatable increments of storage, called physical partitions, which comprise a predetermined number of contiguous addressable blocks, and initially allocating, in response to a request to the operating system, a preselected number of partitions for each group of related information, where the partitions in each group are not necessarily physically contiguous and where the number that is selected is the minimum number of partitions required to store the group of related information. The method further includes the step of automatically allocating one or more additional partitions, located physically on any device, to a previously allocated group of related partitions, dynamically in response to another request of the operating system. A group of partitions that have been allocated to store a group of related information, such as individual files that are related in a hierarchical file system, is called a "Logical Volume". Logical Volumes may be further combined for administration and data management reasons into a "Volume Group".
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公开(公告)号：EP0377970B1
公开(公告)日：1995-08-16
申请号：EP89312896.7
申请日：1989-12-11
发明人： Chang, Albert , Lerom, George Albert , Nicholson, James Otto , O'Quin III, John Claude , O'Quin II, John Thomas
IPC分类号： G06F12/08
CPC分类号： G06F12/084
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3.发明授权Virtual memory address translation mechanism with controlled data persistence 失效具有受控数据持续性的虚拟存储器地址翻译机制
公开(公告)号：EP0113240B1
公开(公告)日：1991-06-05
申请号：EP83307846.2
申请日：1983-12-22
发明人： Chang, Albert , Cocke, John , Mergen, Mark , Radin, George
IPC分类号： G06F12/10
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0781 , G06F12/1036 , G06F12/1475 , G06F2212/683
摘要： A virtual memory address translation mechanism is provided for converting virtual memory addresses provided by a CPU into real memory addresses within page frames in a large hierachial memories wherein the real memory space is substantially smaller than the scope of the virtual memory. The conversion or translation mechanism includes a combined table in the memory which includes a first list covering the respective virtual address of each memory address (Inverted Page or IPT) and a second list connecting each of a plurality of hashed addresses with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address (Hashed Addressed Table, HAT). The system also has means for hashing a selected virtual address to produce a hashed address. Also included in apparatus for sequentially searching through the linked group of virtual addresses in the combined table until a selected virtual address is located as well as apparatus responsive to the location of a particular selected virtual address for accessing from the first list, the real memory address of the located virtual address.
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公开(公告)号：EP0377970A3
公开(公告)日：1991-03-20
申请号：EP89312896.7
申请日：1989-12-11
发明人： Chang, Albert , Lerom, George Albert , Nicholson, James Otto , O'Quin III, John Claude , O'Quin II, John Thomas
IPC分类号： G06F12/08
CPC分类号： G06F12/084
摘要： A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Access authority is checked to determine whether an input/output device is authorised to access that particular page. If it is not, access is denied. Each input/output device has access to a portion of the cache, so that activity by one device will not interfere with activity by another.
摘要翻译： 用于连接输入/输出总线的输入/输出设备的高速缓存。 输入/输出设备访问系统内存的请求通过缓存。 检查访问权限以确定输入/输出设备是否被授权访问该特定页面。 如果不是，访问被拒绝。 每个输入/输出设备都可以访问高速缓存的一部分，因此一台设备的活动不会干扰另一台设备的活动。
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公开(公告)号：EP0377970A2
公开(公告)日：1990-07-18
申请号：EP89312896.7
申请日：1989-12-11
发明人： Chang, Albert , Lerom, George Albert , Nicholson, James Otto , O'Quin III, John Claude , O'Quin II, John Thomas
IPC分类号： G06F12/08
CPC分类号： G06F12/084
摘要： A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Access authority is checked to determine whether an input/output device is authorised to access that particular page. If it is not, access is denied. Each input/output device has access to a portion of the cache, so that activity by one device will not interfere with activity by another.
摘要翻译： 用于连接到输入/输出总线的输入/输出设备的缓存。 通过输入/输出设备访问系统内存的请求通过缓存。 检查访问权限以确定输入/输出设备是否被授权访问该特定页面。 如果不是，访问被拒绝。 每个输入/输出设备都可以访问高速缓存的一部分，因此一个设备的活动不会影响另一个设备的活动。
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公开(公告)号：EP0372779A2
公开(公告)日：1990-06-13
申请号：EP89312293.7
申请日：1989-11-27
CPC分类号： G06F12/08 , G06F12/1009
摘要： Multiple external page table (XPT) structure geometries provide efficient organisation and management of paged, segmented virtual memory systems. First and second small XPT geometries are provided for file mapping of files of a predetermined size for code segments, and file mapping of files exceeding the predetermined size for process private segments, respectively. A large XPT geometry is for working storage segments containing shared library routines. A uniform addressing scheme accesses page state information for second small and large XPT geometries having root blocks. Selected XPT structure direct blocks are pre-allocated for large XPT structures for address ranges to be referenced to reduce page faults.
摘要翻译： 多个外部页表（XPT）结构几何提供分页，分段虚拟内存系统的有效组织和管理。 第一和第二小XPT几何被提供用于代码片段的预定大小的文件的文件映射以及超过预定大小的文件对于处理专用段的文件映射。 大型XPT几何体用于包含共享库例程的工作存储段。 均匀寻址方案访问具有根块的第二个小型和大型XPT几何体的页面状态信息。 所选的XPT结构直接块预分配给大型XPT结构，以引用地址范围以减少页面错误。
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7.发明公开Virtual memory address translation mechanism with controlled data persistence 失效具有受控数据持续性的虚拟存储器地址翻译机制
公开(公告)号：EP0113240A3
公开(公告)日：1987-02-04
申请号：EP83307846
申请日：1983-12-22
发明人： Chang, Albert , Cocke, John , Mergen, Mark , Radin, George
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0781 , G06F12/1036 , G06F12/1475 , G06F2212/683
摘要： A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory functions such as journalling. The address translation function comprises two steps, the first comprising converting the virtual address into a second virtual address or an effective address and finally the step of converting the effective address into a real memory address. The first step utilizes a set of special registers addressable by a small field of the CPU generated virtual address which converts the virtual address into an expanded form. The second or effective address is then used as the subject of the second or address translation step. To greatly enhance the translation of frequently used virtual addresses, a special set of translation tables referred to herein as a Translation Look-Aside, Buffer (TLB) contain current effective to real address translations for use where frequently referenced addresses are requested. The TLBs are addressed using a subset of the effective address whereupon the contents of the addressed TLB is examined for a match with the effective address. If the addresses match a successful address translation is possible and the real address stored in the address field of the TLB is available for system use. If the desired effective address is not present in the TLB, the page frame tables stored in main memory are accessed and searched for the desired effective address and if found the associated real address is accessed. Further a special data field is provided in both the TLBs and the page frame tables in main memory wherein a bit is provided for each line in the referenced page at a given effective to real address translation which bits may be used to indicate when a line of data has been accessed or altered.
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8.发明授权Interrupt requests serializing in a virtual memory data processing system 失效在与虚拟存储器的数据处理系统的中断请求的序列化。
公开(公告)号：EP0239181B1
公开(公告)日：1994-12-07
申请号：EP87300111.9
申请日：1987-01-08
发明人： Chang, Albert , Mergen, Mark Frederick , O'Quin II, John Thomas , O'Quin III, John Claude , Rogers, Mark Douglas
CPC分类号： G06F9/4812 , G06F12/10
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9.发明授权A system and method for using cached data at a local node after re-opening a file at a remote node in a distributed networking environment 失效装置和用于根据在分布式网络中的远程节点的重新打开文件在本地网络节点使用该缓存数据的方法。
公开(公告)号：EP0278317B1
公开(公告)日：1994-06-01
申请号：EP88101094.6
申请日：1988-01-26
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , Y10S707/99952
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公开(公告)号：EP0372779A3
公开(公告)日：1991-04-17
申请号：EP89312293.7
申请日：1989-11-27
CPC分类号： G06F12/08 , G06F12/1009
摘要： Multiple external page table (XPT) structure geometries provide efficient organisation and management of paged, segmented virtual memory systems. First and second small XPT geometries are provided for file mapping of files of a predetermined size for code segments, and file mapping of files exceeding the predetermined size for process private segments, respectively. A large XPT geometry is for working storage segments containing shared library routines. A uniform addressing scheme accesses page state information for second small and large XPT geometries having root blocks. Selected XPT structure direct blocks are pre-allocated for large XPT structures for address ranges to be referenced to reduce page faults.
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