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公开(公告)号：EP0351955B1
公开(公告)日：1995-09-20
申请号：EP89306227.3
申请日：1989-06-20
发明人： Curran, Brian William , D'Onofrio, Joseph Michael , Fuqua, Richard Nickels , Herzl, Robert Dov , Milich, Louis James , Moore, Paul Milton , Temple, Joseph Lester, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
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公开(公告)号：EP0473311A2
公开(公告)日：1992-03-04
申请号：EP91307331.8
申请日：1991-08-09
IPC分类号： G11C11/408 , G11C8/00
CPC分类号： G11C11/408 , G06F12/0215 , G11C8/00
摘要： Improved memory access is provided for use when addressing dynamic random access modules (DRAMs). Both the memory contoller and the main memory hardware remember the row address of the last access. The main memory hardware redrives that row address to the DRAMs after completion of an access, and the memory controller compares each new row address with the row address of the last access, allowing the DRAM to be accessed immediately if the two addresses are the same by activating the Row Address Strobe (RAS).
摘要翻译： 提供了改进的存储器访问，用于寻址动态随机存取模块（DRAM）。 存储器轮廓器和主存储器硬件都记住最后访问的行地址。 主存储器硬件在完成访问之后将行地址重新发送到DRAM，并且存储器控制器将每个新的行地址与最后访问的行地址进行比较，从而允许如果两个地址相同，则立即访问DRAM 激活行地址选通（RAS）。
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公开(公告)号：EP0351955A3
公开(公告)日：1991-07-17
申请号：EP89306227.3
申请日：1989-06-20
发明人： Curran, Brian William , D'Onofrio, Joseph Michael , Fuqua, Richard Nickels , Herzl, Robert Dov , Milich, Louis James , Moore, Paul Milton , Temple, Joseph Lester, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： An improved multiprocessor system of the type including a plurality of processors and an array of memories interconnected by an interrogation logic where the processors have a store-in cache is presented. In such processors the most recent copy of the data does not always reside in the memories but can reside in a processor's cache necessitating cross-interrogation producing system delays. These delays are reduced by a fetch buffer selectively coupled to each memory for holding data before cross-interrogation and other checks are complete.
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公开(公告)号：EP0473311A3
公开(公告)日：1992-12-30
申请号：EP91307331.8
申请日：1991-08-09
IPC分类号： G11C11/408 , G11C8/00
CPC分类号： G11C11/408 , G06F12/0215 , G11C8/00
摘要： Improved memory access is provided for use when addressing dynamic random access modules (DRAMs). Both the memory contoller and the main memory hardware remember the row address of the last access. The main memory hardware redrives that row address to the DRAMs after completion of an access, and the memory controller compares each new row address with the row address of the last access, allowing the DRAM to be accessed immediately if the two addresses are the same by activating the Row Address Strobe (RAS).
摘要翻译： 为寻址动态随机访问模块（DRAM）时提供了改进的内存访问。 内存控制器和主内存硬件都记住上次访问的行地址。 主存储器硬件在访问完成后将该行地址重新分配给DRAM，并且存储器控制器将每个新的行地址与最后一次访问的行地址进行比较，如果两个地址相同，则允许DRAM立即被访问 激活行地址选通（RAS）。
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5.发明公开Multiprocessor systems with cross-interrogated store-in-caches 失效Mehrprozessoranordnungen mit kreuzweise abgefragten Schreib-in-Cachespeichern。
公开(公告)号：EP0351955A2
公开(公告)日：1990-01-24
申请号：EP89306227.3
申请日：1989-06-20
发明人： Curran, Brian William , D'Onofrio, Joseph Michael , Fuqua, Richard Nickels , Herzl, Robert Dov , Milich, Louis James , Moore, Paul Milton , Temple, Joseph Lester, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： An improved multiprocessor system of the type including a plurality of processors and an array of memories interconnected by an interrogation logic where the processors have a store-in cache is presented. In such processors the most recent copy of the data does not always reside in the memories but can reside in a processor's cache necessitating cross-interrogation producing system delays. These delays are reduced by a fetch buffer selectively coupled to each memory for holding data before cross-interrogation and other checks are complete.
摘要翻译： 提出了一种类型的改进的多处理器系统，其包括多个处理器和通过询问逻辑互连的存储器阵列，其中处理器具有存储高速缓存。 在这样的处理器中，数据的最新副本并不总是驻留在存储器中，而是驻留在处理器的高速缓存中，因此需要交叉询问来产生系统延迟。 通过选择性地耦合到每个存储器的获取缓冲器来减少这些延迟，用于在交叉询问之前保持数据并且其他检查完成。
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公开(公告)号：EP0473311B1
公开(公告)日：1996-07-17
申请号：EP91307331.8
申请日：1991-08-09
IPC分类号： G11C11/408 , G11C8/00
CPC分类号： G11C11/408 , G06F12/0215 , G11C8/00
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公开(公告)号：EP0473302A3
公开(公告)日：1992-06-03
申请号：EP91307244.3
申请日：1991-08-07
CPC分类号： G06F12/0215
摘要： A programmable memory controller communicates starting word transfer information with fetch column addresses to assist memory support circuitry interfacing with page mode dynamic random access memory (DRAM) modules. This transfer information is normally provided to the memory support circuitry just before selection of the starting transfer data word from the fetch data line buffer. Memory latency can be reduced when transfer information is available to the support circuitry as it drives column addresses and/or column address strobe signals to the DRAMs.
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8.发明公开Memory device with improved means for controlling data transfer 失效Speithererichtung mit Mitteln zurDatenübertragungssteuerung。
公开(公告)号：EP0473302A2
公开(公告)日：1992-03-04
申请号：EP91307244.3
申请日：1991-08-07
CPC分类号： G06F12/0215
摘要： A programmable memory controller communicates starting word transfer information with fetch column addresses to assist memory support circuitry interfacing with page mode dynamic random access memory (DRAM) modules. This transfer information is normally provided to the memory support circuitry just before selection of the starting transfer data word from the fetch data line buffer. Memory latency can be reduced when transfer information is available to the support circuitry as it drives column addresses and/or column address strobe signals to the DRAMs.
摘要翻译： 可编程存储器控制器将起始字传输信息与提取列地址进行通信，以协助与页模式动态随机存取存储器（DRAM）模块接口的存储器支持电路。 通常，在从提取数据行缓冲器选择起始传送数据字之前，该传送信息通常被提供给存储器支持电路。 当传输信息可用于支持电路，因为它将列地址和/或列地址选通信号驱动到DRAM时，可以减少存储器延迟。
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