公开(公告)号：EP0351955B1

公开(公告)日：1995-09-20

申请号：EP89306227.3

申请日：1989-06-20

申请人： International Business Machines Corporation

发明人： Curran, Brian William ,  D'Onofrio, Joseph Michael ,  Fuqua, Richard Nickels ,  Herzl, Robert Dov ,  Milich, Louis James ,  Moore, Paul Milton ,  Temple, Joseph Lester, III

IPC分类号： G06F12/08

CPC分类号： G06F12/0817

公开(公告)号：EP0351955A3

公开(公告)日：1991-07-17

申请号：EP89306227.3

申请日：1989-06-20

申请人： International Business Machines Corporation

发明人： Curran, Brian William ,  D'Onofrio, Joseph Michael ,  Fuqua, Richard Nickels ,  Herzl, Robert Dov ,  Milich, Louis James ,  Moore, Paul Milton ,  Temple, Joseph Lester, III

IPC分类号： G06F12/08

CPC分类号： G06F12/0817

摘要： An improved multiprocessor system of the type including a plurality of processors and an array of memories interconnected by an interrogation logic where the processors have a store-in cache is presented. In such processors the most recent copy of the data does not always reside in the memories but can reside in a processor's cache necessitating cross-interrogation producing system delays. These delays are reduced by a fetch buffer selectively coupled to each memory for holding data before cross-interrogation and other checks are complete.

公开(公告)号：EP0351955A2

公开(公告)日：1990-01-24

申请号：EP89306227.3

申请日：1989-06-20

申请人： International Business Machines Corporation

发明人： Curran, Brian William ,  D'Onofrio, Joseph Michael ,  Fuqua, Richard Nickels ,  Herzl, Robert Dov ,  Milich, Louis James ,  Moore, Paul Milton ,  Temple, Joseph Lester, III

IPC分类号： G06F12/08

CPC分类号： G06F12/0817

摘要： An improved multiprocessor system of the type including a plurality of processors and an array of memories interconnected by an interrogation logic where the processors have a store-in cache is presented. In such processors the most recent copy of the data does not always reside in the memories but can reside in a processor's cache necessitating cross-interrogation producing system delays. These delays are reduced by a fetch buffer selectively coupled to each memory for holding data before cross-interrogation and other checks are complete.

摘要翻译： 提出了一种类型的改进的多处理器系统，其包括多个处理器和通过询问逻辑互连的存储器阵列，其中处理器具有存储高速缓存。 在这样的处理器中，数据的最新副本并不总是驻留在存储器中，而是驻留在处理器的高速缓存中，因此需要交叉询问来产生系统延迟。 通过选择性地耦合到每个存储器的获取缓冲器来减少这些延迟，用于在交叉询问之前保持数据并且其他检查完成。