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    Multiprocessor systems with cross-interrogated store-in-caches
    3.
    发明公开
    Multiprocessor systems with cross-interrogated store-in-caches 失效
    Mehrprozessoranordnungen mit kreuzweise abgefragten Schreib-in-Cachespeichern。

    公开(公告)号：EP0351955A2

    公开(公告)日：1990-01-24

    申请号：EP89306227.3

    申请日：1989-06-20

    申请人： International Business Machines Corporation

    发明人： Curran, Brian William ,  D'Onofrio, Joseph Michael ,  Fuqua, Richard Nickels ,  Herzl, Robert Dov ,  Milich, Louis James ,  Moore, Paul Milton ,  Temple, Joseph Lester, III

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0817

    摘要： An improved multiprocessor system of the type including a plurality of processors and an array of memories interconnected by an interrogation logic where the processors have a store-in cache is presented. In such processors the most recent copy of the data does not always reside in the memories but can reside in a processor's cache necessitating cross-interrogation producing system delays. These delays are reduced by a fetch buffer selectively coupled to each memory for holding data before cross-interrogation and other checks are complete.

    摘要翻译： 提出了一种类型的改进的多处理器系统，其包括多个处理器和通过询问逻辑互连的存储器阵列，其中处理器具有存储高速缓存。 在这样的处理器中，数据的最新副本并不总是驻留在存储器中，而是驻留在处理器的高速缓存中，因此需要交叉询问来产生系统延迟。 通过选择性地耦合到每个存储器的获取缓冲器来减少这些延迟，用于在交叉询问之前保持数据并且其他检查完成。

    Multiprocessor data processing with cross interrogate synchronization mechanism
    4.
    发明公开
    Multiprocessor data processing with cross interrogate synchronization mechanism 失效
    采用交叉询问同步机制的多处理器数据处理

    公开(公告)号：EP0531004A3

    公开(公告)日：1994-03-02

    申请号：EP92307485.0

    申请日：1992-08-14

    申请人： International Business Machines Corporation

    发明人： Herzl, Robert Dov ,  Quinn, Linda Legault ,  Schroter, Russell Evan

    IPC分类号： G06F13/14 ,  G06F12/08

    CPC分类号： G06F12/0828 ,  G06F12/0822 ,  G06F13/14

    摘要： A mechanism prioritizes cross interrogate requests between multiple requestors in a multi-processor system where the delay due to cable length interconnecting requestors results in requests not being received within one machine cycle. Local and remote cross interrogate (XI) requests are latched up in storage control element (SCE) temporary registers before being prioritized. The local request is staged in a local delay register. The local request is selected from the local delay register by synchronization control logic, instead of the temporary register, when the remote request is issued one cycle earlier than the local request, or when both local and remote requests are issued at the same time, but the remote requests is from a master SCE. The staging of the local requests can be extended to multiple cycles, corresponding to the length of the cables between SCEs.

    摘要翻译： 一种机制优先于多处理器系统中的多个请求者之间的交叉询问请求，其中由于电缆长度互连请求者的延迟导致在一个机器周期内未接收到请求。 本地和远程交叉询问（XI）请求在优先化之前锁存在存储控制元素（SCE）临时寄存器中。 本地请求在本地延迟寄存器中进行。 当远程请求比本地请求提前一个周期发出时，或者同时发出本地请求和远程请求时，本地请求通过同步控制逻辑而不是临时寄存器从本地延迟寄存器中选择，但是 远程请求来自主SCE。 本地请求的分段可以延长到多个周期，对应于SCE之间的电缆长度。

    Data processing with bidirectional data bus reservation priority controls
    5.
    发明公开
    Data processing with bidirectional data bus reservation priority controls 失效
    Datenverarbeitung mitPrioritätssteuerungenfürReservierung eines bidirektionellen Datenbusses。

    公开(公告)号：EP0531003A1

    公开(公告)日：1993-03-10

    申请号：EP92307484.3

    申请日：1992-08-14

    申请人： International Business Machines Corporation

    发明人： Herzl, Robert Dov ,  Schroter, David Andres

    IPC分类号： G06F13/37 ,  G06F13/18

    CPC分类号： G06F13/37 ,  G06F13/18

    摘要： A data bus reservation system controls data transfer between storage control elements (SCEs) in a multi-processor system. Each SCE is assigned a default bidirectional (BIDI) data bus for transfer of data. If a request for data transfer is made and the default data bus is already reserved, then the requestor must wait for the data bus to become available and a token passed to the requestor. When the token is passed to the requestor, it has priority to reserve an available data bus. The token is passed to a different processor with each machine cycle. Additionally, there is error checking logic in which checks a confirmation sent to the other SCE when the BIDI bus has been reserved.

    摘要翻译： 数据总线预留系统控制多处理器系统中的存储控制元件（SCE）之间的数据传输。 为每个SCE分配一个用于传输数据的默认双向（BIDI）数据总线。 如果进行了数据传输请求，并且默认数据总线已被保留，则请求者必须等待数据总线变为可用，并将令牌传递给请求者。 当令牌传递给请求者时，优先保留可用的数据总线。 每个机器周期将令牌传递给不同的处理器。 另外，存在错误检查逻辑，其中当保留BIDI总线时检查确认发送到其他SCE。

    Multiprocessor data processing with cross interrogate synchronization mechanism
    6.
    发明公开
    Multiprocessor data processing with cross interrogate synchronization mechanism 失效
    Multiprozessordatenverarbeitung mitSynchronisationsgerätfürBefragungen。

    公开(公告)号：EP0531004A2

    公开(公告)日：1993-03-10

    申请号：EP92307485.0

    申请日：1992-08-14

    申请人： International Business Machines Corporation

    发明人： Herzl, Robert Dov ,  Quinn, Linda Legault ,  Schroter, Russell Evan

    IPC分类号： G06F13/14 ,  G06F12/08

    CPC分类号： G06F12/0828 ,  G06F12/0822 ,  G06F13/14

    摘要： A mechanism prioritizes cross interrogate requests between multiple requestors in a multi-processor system where the delay due to cable length interconnecting requestors results in requests not being received within one machine cycle. Local and remote cross interrogate (XI) requests are latched up in storage control element (SCE) temporary registers before being prioritized. The local request is staged in a local delay register. The local request is selected from the local delay register by synchronization control logic, instead of the temporary register, when the remote request is issued one cycle earlier than the local request, or when both local and remote requests are issued at the same time, but the remote requests is from a master SCE. The staging of the local requests can be extended to multiple cycles, corresponding to the length of the cables between SCEs.

    摘要翻译： 一种机制优先考虑多处理器系统中的多个请求者之间的交叉询问请求，其中由于电缆长度互连请求者的延迟导致在一个机器周期内未被接收的请求。 本地和远程交叉询问（XI）请求被优先锁存在存储控制元件（SCE）临时寄存器中。 本地请求在本地延迟寄存器中进行。 本地请求是通过同步控制逻辑从本地延迟寄存器中选择的，而不是临时寄存器，当远程请求比本地请求提前一个周期，或同时发出本地和远程请求时， 远程请求来自主SCE。 本地请求的分期可以扩展到多个周期，对应于SCE之间的电缆长度。